Display substrate and display device

Abstract

Display substrate and display device. The present invention relates to a display device and substrate comprising a substrate base (50) and multiple subpixels arranged in a matrix on the substrate base (50). The subpixel comprises: data line patterns (data1, data2) extending in a first direction (y); a portion of a power line pattern (vdd) extending in the first direction (y); and a subpixel drive circuit comprising two switching transistors (t4, t5), a drive transistor (t3), and a storage capacitor (cst). A first electrode plate (cst1) of the storage capacitor (cst) is coupled with a gate electrode (203g) of the drive transistor (t3). A second electrode plate (cst2) of the storage capacitor (cst) is coupled with the power line pattern (vdd).The second electrodes (d4, d5) of the two switching transistors (t4, t5) are both coupled with a first electrode (s3) of the drive transistor (t3). The orthographic projection of the second electrode (d4, d5) of at least one of the two switching transistors (t4, t5) onto the substrate base (50) at least partially overlaps with the orthographic projection of the power line pattern (vdd) onto the substrate base (50), and at least partially overlaps with an orthographic projection of the second electrode plate (cst2) of the storage capacitor (cst) onto the substrate base (50).

Description

1 / 112 Display substrate and display device cross-reference upon request.

[0001] This application claims priority under the PCT Application Application number PCT / CN2019 / 121948 filed on November 29, 2019, the description of which is incorporated herein in its entirety by reference. FIELD OF TECHNIQUE

[0002] The present invention relates to the field of display technology, specifically to a display substrate and a display device. BACKGROUND

[0003] Light Emitting Diode display products Organic LEDs have been widely applied in various fields due to advantages such as high brightness, low power consumption, fast response, high resolution, excellent flexibility, and high luminous efficiency.

[0004] Along with the expansion of the application of OLED display products, the display quality of OLED display products is in high demand. There are several factors that affect the display quality of display products, and as one of the important factors, the crosshair generated due to a pixel circuit in the display product has attracted increasing attention. SUMMARY

[0005] One object of the present description is to provide a display substrate and a display device.

[0006] In one aspect, the present description provides in some embodiments a display substrate comprising a base and a plurality of subpixels arranged on the base in a matrix form, wherein the subpixel includes: a data line pattern that extends into a first Petition 870260037267, dated 04 / 22 / 2026, page 6 / 259 2 / 112 direction; a first shielding member, wherein at least a portion of the first shielding member extends in the first direction; and a drive transistor, a first transistor coupled to a gate electrode of the drive transistor, and a second shielding member coupled to the first shielding member.The first transistor is of a dual-gate structure; the first transistor includes a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern; the sixth conductor pattern is coupled to the fourth semiconductor pattern and the fifth semiconductor pattern; and a second electrode of the driver transistor is coupled to the fourth semiconductor pattern or the fifth semiconductor pattern; an orthogonal projection of the second shield member onto the base at least partially overlaps an orthogonal projection of the sixth conductor pattern onto the base; at least a portion of the first shield member is located between a second electrode of the driver transistor and a data line pattern of an adjacent subpixel.

[0007] Optionally, the second armor member is positioned closer to the base than the first armor member.

[0008] Optionally, an area of ​​overlap between an orthogonal projection of the first shield member onto the base and an orthogonal projection of the second electrode of the drive transistor onto the base is E1, a portion of the orthogonal projection of the second electrode of the drive transistor onto the base does not overlap the orthogonal projection of the first shield member onto the base, an area of ​​the portion of the orthogonal projection of the second electrode of the drive transistor onto the base that does not overlap the orthogonal projection of the first shield member onto the base is E2, and Petition 870260037267, dated 04 / 22 / 2026, page 7 / 259 3 / 112 E1 <E2.

[0009] Optionally, in a second direction, a minimum straight-line distance between the orthogonal projection of the second electrode of the drive transistor onto the base and the orthogonal projection of the first shield member onto the base is L1, a minimum straight-line distance between the orthogonal projection of the second electrode of the drive transistor onto the base and an orthogonal projection of the data line pattern of the adjacent subpixel onto the base is L2, and L1 <L2.

[0010] Optionally, one channel length of the drive transistor is L3, and L1 <L2<L3.

[0011] Optionally, a minimum straight-line distance between the second electrode of the drive transistor and the data line pattern of the adjacent subpixel is L4, a minimum straight-line distance between the second electrode of the drive transistor and the first shield member is L5, and L5 <L4.

[0012] Optionally, the subpixel also includes a connecting line, the gate electrode of the drive transistor is coupled to a second electrode of the first transistor via the connecting line; The orthogonal projection of the second shielding member onto the base is located between an orthogonal projection of one end of the connecting line coupled to the second electrode of the first transistor onto the base and the orthogonal projection of the data line pattern of the adjacent subpixel onto the base.

[0013] Optionally, in the first direction, the length of the first shielding member is greater than the length of the connecting line.

[0014] Optionally, a length of a portion of the second electrode of the drive transistor that does not overlap the first. Petition 870260037267, dated 04 / 22 / 2026, page 8 / 259 4 / 112 of the armor member in the first direction is L6, the length of the first armor member in the first direction is L7, and L6 <L7.

[0015] Optionally, a gap is provided between the orthogonal projection of the first shield member onto the base and the orthogonal projection of the second electrode of the drive transistor onto the base.

[0016] Optionally, the subpixel further includes a fourth transistor, a first electrode of the fourth transistor is coupled in the data line pattern, and a second electrode of the fourth transistor is coupled to a first electrode of the drive transistor; the orthogonal projection of the second shield member onto the base does not overlap an orthogonal projection of a fourth transistor of the adjacent subpixel onto the base.

[0017] Optionally, the first shielding member and the second shielding member are configured to receive a first fixed potential signal.

[0018] Optionally, the subpixel also includes a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate, the first electrode plate is coupled to the gate electrode of the drive transistor, the second electrode plate is configured to receive a second fixed potential signal; A gap is provided between an orthogonal projection of the second electrode plate onto the base and the orthogonal projection of the first shielding member onto the base; The orthogonal projection of the second electrode of the drive transistor onto the base includes a portion within the gap.

[0019] Optionally, the first fixed potential signal is the same as the second fixed potential signal.

[0020] Optionally, the second electrode of the transistor of Petition 870260037267, dated 04 / 22 / 2026, page 9 / 259 5 / 112 drive is positioned closer to the base than the first armor member and the second armor member.

[0021] Optionally, an active layer of the first transistor is arranged in the same layer as, and formed integrally with, an active layer of the drive transistor.

[0022] Optionally, a minimum straight-line distance between the first shielding member and the second electrode of the drive transistor is greater than a minimum straight-line distance between the second shielding member and the sixth conductor pattern.

[0023] Optionally, the subpixel also includes: a reset signal line pattern and a startup signal line pattern, wherein each of the reset signal line patterns and the startup signal line pattern extends in a second direction that intersects the first direction; a second transistor, wherein one gate electrode of the second transistor is coupled to the reset signal line pattern, one first electrode of the second transistor is coupled to the initialization signal line pattern, and one second electrode of the second transistor is coupled to the gate electrode of the drive transistor.

[0024] Optionally, an orthogonal projection of a contact portion of the second shielding member in contact with the first shielding member on the base does not overlap an orthogonal projection of an active layer of the second transistor on the base; a distance between the contact portion and the sixth conductor pattern is less than a distance between the contact portion and the second electrode of the drive transistor; a distance between the orthogonal projection of the contact portion on the base and the orthogonal projection of the sixth conductor pattern on the base is less than a distance between the orthogonal projection of the contact portion on the base and the Petition 870260037267, dated 04 / 22 / 2026, page 10 / 259 6 / 112 Orthogonal projection of the data line pattern onto the base.

[0025] Optionally, the subpixel also includes: a light emission control signal line pattern and a power line pattern, wherein the light emission control signal line pattern extends in the second direction, the power line pattern includes a portion that extends in the first direction; a fifth transistor, in which a gate electrode of the fifth transistor is coupled to the light emission control signal line pattern, a first electrode of the fifth transistor is coupled to the power supply line pattern, and a second electrode of the fifth transistor is coupled to the first electrode of the drive transistor.

[0026] Optionally, the subpixel also includes a light-emitting element and a sixth transistor, a gate electrode of the sixth transistor is coupled to the light-emitting control signal line pattern, a first electrode of the sixth transistor is coupled to the second electrode of the drive transistor, and a second electrode of the sixth transistor is coupled to the light-emitting element.

[0027] In another aspect, the present description provides in some embodiments a display substrate, which includes a base and a plurality of subpixels arranged on the base in a matrix form, wherein the subpixel includes: a data line pattern that extends in a first direction; a first shielding member, wherein at least a portion of the first shielding member extends in the first direction; and a drive transistor, a first transistor coupled to a gate electrode of the drive transistor, and a Petition 870260037267, dated 04 / 22 / 2026, p. 11 / 259 7 / 112 second shielding member coupled to the first shielding member. The first transistor is of a double-gate structure, the first transistor includes a fourth semiconductor pattern, a fifth semiconductor pattern and a sixth conductor pattern, the sixth conductor pattern is coupled to the fourth semiconductor pattern and the fifth semiconductor pattern, and a second electrode of the driving transistor is coupled to the fourth semiconductor pattern or the fifth semiconductor pattern; a straight-line distance between a contact portion of the second shielding member in contact with the first shielding member and the sixth conductor pattern is less than a straight-line distance between the contact portion and the second electrode of the driving transistor;and a distance between an orthogonal projection of the contact portion of the second shielding member in contact with the first shielding member on the base and an orthogonal projection of the sixth conductor pattern on the base is less than a distance between the orthogonal projection of the contact portion on the base and an orthogonal projection of the data line pattern on the base.

[0028] Optionally, the second shielding member is arranged closer to the base than the first shielding member.

[0029] Optionally, an area of ​​overlap between an orthogonal projection of the first shielding member onto the base and an orthogonal projection of the second electrode of the drive transistor onto the base is E1, a portion of the orthogonal projection of the second electrode of the drive transistor onto the base does not overlap the orthogonal projection of the first shielding member onto the base, an area of ​​the portion of the orthogonal projection of the second electrode of the drive transistor onto the base that does not overlap the orthogonal projection of the first shielding member onto the base is E2, and E1 <E2.

[0030] Optionally, in a second direction, a distance in Petition 870260037267, dated 04 / 22 / 2026, page 12 / 259 8 / 112 minimum straight line distance between the orthogonal projection of the second electrode of the drive transistor onto the base and the orthogonal projection of the first shield member onto the base is L1, a minimum straight line distance between the orthogonal projection of the second electrode of the drive transistor onto the base and an orthogonal projection of the data line pattern of an adjacent subpixel onto the base is L2, and L1 <L2.

[0031] Optionally, a length of one channel of the drive transistor in a second direction is L3, and L1 <L2<L3.

[0032] Optionally, a minimum straight-line distance between the second electrode of the drive transistor and the data line pattern of the adjacent subpixel is L4, a minimum straight-line distance between the second electrode of the drive transistor and the first shield member is L5, and L5 <L4.

[0033] Optionally, the subpixel also includes a connecting line, the gate electrode of the drive transistor is coupled to a second electrode of the first transistor via the connecting line; the orthogonal projection of the second shield member onto the base is located between an orthogonal projection of one end of the connecting line coupled to the second electrode of the first transistor onto the base and the orthogonal projection of the data line pattern of the adjacent subpixel onto the base.

[0034] Optionally, in the first direction, the length of the first shielding member is greater than the length of the connecting line.

[0035] Optionally, a length of a portion of the second electrode of the drive transistor that does not overlap the first shielding member in the first direction is L6, a length of the first shielding member in the first direction is L7, and L6 <L7.

[0036] Optionally, a gap is provided between the projection Petition 870260037267, dated 04 / 22 / 2026, page 13 / 259 9 / 112 orthogonal projection of the first shielding member onto the base and the orthogonal projection of the second electrode of the drive transistor onto the base.

[0037] Optionally, the subpixel also includes a fourth transistor, a first electrode of the fourth transistor is coupled to the data line pattern, and a second electrode of the fourth transistor is coupled to a first electrode of the drive transistor; the orthogonal projection of the second shield member onto the base does not overlap an orthogonal projection of a fourth transistor of the adjacent subpixel onto the base.

[0038] Optionally, the first shielding member and the second shielding member are configured to receive a first fixed potential signal.

[0039] Optionally, the subpixel also includes a storage capacitor, the storage capacitor includes a first electrode plate and a second electrode plate, the first electrode plate is coupled to the gate electrode of the drive transistor, the second electrode plate is configured to receive a second fixed potential signal; a gap is provided between an orthogonal projection of the second electrode plate onto the base and the orthogonal projection of the first shield member onto the base; the orthogonal projection of the second electrode of the drive transistor onto the base includes a portion within the gap.

[0040] Optionally, the first fixed potential signal is the same as the second fixed potential signal.

[0041] Optionally, the second electrode of the drive transistor is positioned closer to the base than the first shield member and the second shield member.

[0042] Optionally, an active layer of the first transistor is arranged in the same layer that is formed integrally Petition 870260037267, dated 04 / 22 / 2026, page 14 / 259 10 / 112 with an active layer of the drive transistor.

[0043] Optionally, a minimum straight-line distance between the first shielding member and the second electrode of the drive transistor is greater than a minimum straight-line distance between the second shielding member and the sixth conductor pattern.

[0044] Optionally, the subpixel also includes: a reset signal line pattern and a startup signal line pattern, wherein each of the reset signal line patterns and the startup signal line pattern extends in a second direction that intersects the first direction; a second transistor, wherein one gate electrode of the second transistor is coupled to the reset signal line pattern, one first electrode of the second transistor is coupled to the initialization signal line pattern, and one second electrode of the second transistor is coupled to the gate electrode of the drive transistor.

[0045] Optionally, an orthogonal projection of a contact portion of the second shielding member in contact with the first shielding member on the base does not overlap an orthogonal projection of an active layer of the second transistor on the base; a minimum straight-line distance between a portion of the first shielding member and the second shielding member is less than a minimum straight-line distance between the data line pattern of the adjacent subpixel and the second shielding member, the portion of the first shielding member extends in the first direction.

[0046] Optionally, the subpixel also includes: a light emission control signal line pattern and a power line pattern, wherein the light emission control signal line pattern extends in the second direction, the pattern of Petition 870260037267, dated 04 / 22 / 2026, page 15 / 259 11 / 112 power line includes a portion that extends in the first direction; a fifth transistor, wherein a gate electrode of the fifth transistor is coupled to the light emission control signal line pattern, a first electrode of the fifth transistor is coupled to the power line pattern, and a second electrode of the fifth transistor is coupled to the first electrode of the drive transistor.

[0047] Optionally, the subpixel also includes a light-emitting element and a sixth transistor, a gate electrode of the sixth transistor is coupled to the light-emitting control signal line pattern, a first electrode of the sixth transistor is coupled to the second electrode of the drive transistor, and a second electrode of the sixth transistor is coupled to the light-emitting element.

[0048] In yet another aspect, the present description provides in some embodiments a display device that includes the aforementioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The following drawings are provided to facilitate understanding of the present description, and constitute a portion of the present description. The exemplary embodiments and their explanation are for illustrative purposes only, but should not be considered as limiting the present description. In these drawings,

[0050] Figure 1 is a schematic view showing a subpixel drive circuit according to an embodiment of the present description;

[0051] Figure 2 is a sequential diagram of the subpixel drive circuit according to an embodiment of the present description;

[0052] Figure 3 is a schematic view showing an early layout of the subpixel drive circuit on a substrate of Petition 870260037267, dated 04 / 22 / 2026, page 16 / 259 12 / 112 display according to an embodiment of the present description;

[0053] Figure 4 is a schematic view showing the first layout of an active film layer according to an embodiment of the present description;

[0054] Figure 5 is a schematic view showing a first layout of a first metal door layer according to an embodiment of the present description;

[0055] Figure 6 is a schematic view showing a first layout of a second metal door layer according to an embodiment of the present description;

[0056] Figure 7 is a schematic view showing a first layout of a source / drain metal layer according to an embodiment of the present description;

[0057] Figure 8 is a cross-sectional view of the display substrate along line A1A2 in Figure 3;

[0058] Figure 9 is a schematic view showing a second layout of the subpixel drive circuit on the display substrate according to an embodiment of the present description;

[0059] Figure 10 is a schematic view showing a third layout of the subpixel drive circuit on the display substrate according to an embodiment of the present description;

[0060] Figure 11 is a schematic view showing a fourth layout of the subpixel drive circuit on the display substrate according to an embodiment of the present description;

[0061] Figure 12 is a schematic view showing a fifth layout of the subpixel drive circuit on the display substrate according to an embodiment of the present description;

[0062] Figure 13 is a sectional view along line B1B2 in Figure 11;

[0063] Figure 14 is a schematic view showing one sixth Petition 870260037267, dated 04 / 22 / 2026, page 17 / 259 13 / 112 layout of the subpixel drive circuit on the display substrate according to an embodiment of the present description;

[0064] Figure 15 is a schematic view showing a first layout of a plurality of subpixels on the display substrate according to an embodiment of the present description;

[0065] Figure 16 is a schematic view showing a seventh layout of the subpixel drive circuit on the display substrate according to an embodiment of the present description;

[0066] Figure 17 is a sectional view along a line C1C2 in Figure 16;

[0067] Figure 18 is a schematic view showing a second layout of the active film layer according to an embodiment of the present description;

[0068] Figure 19 is a schematic view showing an eighth layout of the subpixel drive circuit on the display substrate according to an embodiment of the present description;

[0069] Figure 20 is a schematic view showing a ninth layout of the subpixel drive circuit on the display substrate according to an embodiment of the present description;

[0070] Figure 21 is a schematic view showing a tenth layout of the subpixel drive circuit on the display substrate according to an embodiment of the present description;

[0071] Figure 22 is a sectional view along a line D1D2 in Figure 21;

[0072] Figure 23 is a schematic view showing the layout of a third metallic layer;

[0073] Figure 24 is a schematic view showing a second layout of the plurality of subpixels on the display substrate according to an embodiment of the present description;

[0074] Figure 25 is a schematic view showing a phenomenon Petition 870260037267, dated 04 / 22 / 2026, page 18 / 259 14 / 112 cross-line that occurs for a gate electrode of a drive transistor in the relevant technique;

[0075] Figure 26 is a schematic view showing an eleventh layout of the subpixel drive circuit on the display substrate according to an embodiment of the present description;

[0076] Figure 27 is a schematic view showing a twelfth layout of the subpixel drive circuit on the display substrate according to an embodiment of the present description;

[0077] Figure 28 is a cross-sectional view of two adjacent subpixel drive circuits along a line D1D2 in Figure 21. DETAILED DESCRIPTION

[0078] Further explaining the display substrate and display device provided by the embodiments of the present description, will be described herein in detail together with the drawings.

[0079] In the relevant technique, a crosshair is generated in an OLED display product for various features, and primarily, the crosshair is generated for a drive transistor due to a data line pattern that encircles the drive transistor in a subpixel drive circuit. More specifically, during the layout of the subpixel drive circuit, several transistors that have other functions can be arranged around the drive transistor in the subpixel drive circuit, and these transistors each consist of a plurality of layers of conductive patterns. In addition, several signal line patterns for transmitting different signals are also arranged around the drive transistor.Due to the operation of the subpixel drive circuit, any change in signals in the transistors' conductive patterns and in the signal line patterns can easily lead to line crossover to the drive transistor, and through this... Petition 870260037267, dated 04 / 22 / 2026, page 19 / 259 15 / 112 The operational performance of the drive transistor may be adversely affected.

[0080] Due to the aforementioned problems, it is discovered through study that the crosshair that affects the operational performance of the drive transistor mainly includes the crosshair generated due to coupling between the data line pattern and a gate electrode of the drive transistor, and the crosshair generated due to coupling between the data line pattern and a first electrode of the drive transistor.

[0081] The inventor of the present description has further discovered that a pattern of a fixed potential can be formed on the first electrode of the drive transistor, so as to shield through the pattern in the fixed potential of the first electrode of the drive transistor and reduce the coupling effect between the data line pattern in the vicinity of the first electrode of the drive transistor and the first electrode of the drive transistor, thereby relieving the crosstalk generated by the data line pattern to the drive transistor and improving the display effect of the product display.

[0082] It should be appreciated that a display substrate having a subpixel drive circuit based on 7T1C (i.e., seven thin-film transistors and one capacitor) is involved in one or more embodiments of the present description. In another embodiment, the display substrate may include another different subpixel drive circuit, for example, a subpixel drive circuit that includes more than or less than seven thin-film transistors and one or more capacitors.

[0083] As shown in Figure 1, the present description provides in some embodiments a display substrate which includes a plurality of subpixels. Each subpixel may include a GATE gate line pattern, a first RST1 reset signal line pattern, a Petition 870260037267, dated 04 / 22 / 2026, page 20 / 259 16 / 112 first initialization signal line pattern VINT1, a data line pattern DATA, a light emission control signal pattern EM, a power line pattern VDD, a second reset signal line pattern RST2 and a second initialization signal line pattern VINT2.

[0084] A subpixel drive circuit for each subpixel may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst. In addition, as shown in Figure 1, the subpixel drive circuit may also include a first capacitor C1, which is a parasitic capacitor.

[0085] Taking a subpixel drive circuit as an example, the transistors in the subpixel drive circuit can be P-type transistors. The first transistor T1 can be of a dual-gate structure, a gate electrode 201g of the first transistor T1 can be coupled in the gate line pattern, a source electrode S1 of the first transistor T1 can be coupled to a drain electrode D3 of the third transistor T3, and a drain electrode D1 of the first transistor T1 can be coupled to a gate electrode 203g of the third transistor T3.

[0086] The second transistor T2 can be of a double-gate structure, a gate electrode 202g of the second transistor T2 can be coupled to the first reset signal line pattern RST1, a source electrode S2 of the second transistor T2 can be coupled to the first initialization signal line pattern VINT1, and a drain electrode D2 of the second transistor T2 can be coupled to the gate electrode 203g of the third transistor T3.

[0087] A gate electrode 204g of the fourth transistor T4 can be coupled in the gate line pattern, a source electrode S4 Petition 870260037267, dated 04 / 22 / 2026, page 21 / 259 17 / 112 of the fourth transistor T4 can be coupled to the DATA data line pattern, and a drain electrode D4 of the fourth transistor T4 can be coupled to a source electrode S3 of the third transistor T3.

[0088] A gate electrode 205g of the fifth transistor T5 can be coupled to the EM light emission control signal line pattern, a source electrode S5 of the fifth transistor T5 can be coupled to the VDD power line pattern, and a drain electrode D5 of the fifth transistor T5 can be coupled to the source electrode S3 of the third transistor T3.

[0089] A gate electrode 206g of the sixth transistor T6 can be coupled to the EM light emission control signal line pattern, a source electrode S6 of the sixth transistor T6 can be coupled to the drain electrode D3 of the third transistor T3, and a drain electrode D6 of the sixth transistor T6 can be coupled to an anode of an OLED light-emitting element.

[0090] A gate electrode 207g of the seventh transistor T7 can be coupled to the second reset signal line pattern RST2, a drain electrode D7 of the seventh transistor T7 can be coupled to the anode of the OLED light-emitting element, and a source electrode S7 of the seventh transistor T7 can be coupled to the second initialization signal line pattern VINT2.

[0091] A first electrode plate Cst1 of the storage capacitor Cst can be coupled to the gate electrode 203g of the third transistor T3, and a second electrode plate Cst2 of the storage capacitor Cst can be coupled to the standard power line VDD.

[0092] As shown in Figure 2, during the operation of the subpixel drive circuit with the aforementioned structure, each operating period may include a first reset phase P1, a write compensation phase P2, a second reset phase P3 and Petition 870260037267, dated 04 / 22 / 2026, page 22 / 259 18 / 112 a light emission phase P4.

[0093] In the first reset phase P1, a first reset signal inserted by the first reset signal line pattern RST1 may be at an active level, so as to turn on the second transistor T2. A startup signal from the first startup signal line pattern VINT1 may be inserted into the gate electrode 203g of the third transistor T3, so as to allow a gate voltage to source Vgs held in the third transistor T3 within a previous frame to be zero, thereby resetting the gate electrode 203g of the third transistor T3.

[0094] In the P2 write compensation phase, the first reset signal can be at an inactive level, so as to turn off the second transistor T2. A gate scan signal inserted by the GATE gate line pattern can be at an active level, so as to turn on the first transistor T1 and the fourth transistor T4. A data signal can be written to the DATA data line pattern, and then transmitted to the source electrode S3 of the third transistor T3 via the fourth transistor T4. Furthermore, when the first transistor T1 and the fourth transistor T4 are turned on, the third transistor T3 can be a diode structure, so that the first transistor T1, the third transistor T3 and the fourth transistor T4 can cooperate to compensate for a threshold voltage of the third transistor T3.When a compensation time period is long enough, a potential at the gate electrode 203g of the third transistor T3 can finally reach Vdata+Vth, where Vdata represents a voltage value of the data signal, and Vth represents the threshold voltage of the third transistor T3.

[0095] In the second reset phase P3, the gate scan signal may be at an inactive level, so as to turn off the first transistor T1 and the fourth transistor T4. A second reset signal inserted by the first reset signal line RST2 may be at an active level, so as to turn on the seventh transistor T7. A startup signal of Petition 870260037267, dated 04 / 22 / 2026, p. 23 / 259 The 19 / 112 second standard VINT2 initialization signal line can be transmitted to the anode of the OLED light-emitting element, so as to control the OLED light-emitting element to prevent it from emitting light.

[0096] In the P4 light emission phase, a light emission control signal written in the EM light emission control signal line pattern can be at an active level, so as to turn on the fifth transistor T5 and the sixth transistor T6, thereby transmitting power from the VDD power line pattern to the S3 source electrode of the third transistor T3. Furthermore, the 203g gate electrode of the third transistor T3 is held at Vdata+Vth, so that the third transistor T3 can be turned on, and a gate-to-source voltage of the third transistor T3 can be Vdata+Vth-VDD, where VDD represents a supply voltage value. A leakage current generated according to the gate-to-source voltage can flow to the anode of the corresponding OLED light-emitting element in order to trigger the corresponding OLED light-emitting element to emit light.

[0097] As shown in Figure 3, during the fabrication of the subpixel drive circuit, the film layer layout of the subpixel drive circuit will be described as follows. An active film layer, a gate insulation layer, a first gate metal layer, a first interlayer insulation layer, a second gate metal layer, a second interlayer insulation layer, a first source / drain metal layer, and a third interlayer insulation layer can be laminated on top of each other in this order in a direction away from a base.

[0098] As shown in Figure 4, the active film layer can be used to form a channel region (e.g., 101pg to 107pg), a source electrode formation region (e.g., 101ps to 107ps), and a drain electrode formation region (e.g., 101ps to 107ps). Petition 870260037267, dated 04 / 22 / 2026, page 24 / 259 20 / 112 example, 101pd to 107pd) of each transistor in the subpixel drive circuit. Due to a doping effect, the active film layers corresponding to the source electrode formation region and the drain electrode formation region may have a higher electrical conductivity than the active film layer corresponding to the channel region. The active film layer may be made of amorphous silicon, polysilicon, or an oxide semiconductor material. It should be noted that the source electrode formation region and the drain electrode formation region may each be a region doped with n-type or p-type impurities.

[0099] Furthermore, it should be appreciated that the active film layers corresponding to the source electrode formation region and the drain electrode formation region can directly serve as the corresponding source electrode and drain electrode; or the source electrode in contact with the source electrode formation region can be made of a metallic material, and the drain electrode in contact with the drain electrode formation region can be made of a metallic material.

[0100] As shown in Figure 5, the first metallic gate layer can be used to form the gate electrodes (e.g., 201g to 207g) of the transistors in the subpixel drive circuit, as well as the GATE gate line pattern, the EM light emission control signal line pattern, the first RST1 reset signal line pattern, and the second RST2 reset signal line pattern of the display substrate. The 203g gate electrode of the third transistor T3 in each subpixel drive circuit can be reused as the first electrode plate Cst1 of the storage capacitor Cst in the subpixel drive circuit.

[0101] As shown in Figure 6, the second metal gate layer can be used to form the second electrode plate Cst2 Petition 870260037267, dated 04 / 22 / 2026, page 25 / 259 21 / 112 of the storage capacitor Cst, as well as the first initialization signal line pattern VINT1 and the second initialization signal line pattern VINT2 of the display substrate.

[0102] As shown in Figures 1, 3 and 7, the first metallic source / drain layer can be used to form the source electrodes (e.g., S1 to S7) and the drain electrodes (e.g., D1 to D7) of the transistors in the subpixel drive circuit, as well as the data line pattern (e.g., DATA1 and DATA2) and the VDD power line pattern of the display substrate.

[0103] More specifically, referring to Figures 3 and 7-10 again, the gate electrode 201g of the first transistor T1 may cover a first channel region 101pg, the source electrode S1 of the first transistor T1 may be located in a first source electrode formation region 101ps, and the drain electrode D1 of the first transistor T1 may be located in a first drain electrode formation region 101pd.

[0104] The gate electrode 202g of the second transistor T2 can cover a second 102pg channel region, the source electrode S2 of the second transistor T2 can be located in a second 102ps source electrode formation region, and the drain electrode D2 of the second transistor T2 can be located in a second 102pd drain electrode formation region.

[0105] The gate electrode 203g of the third transistor T3 can cover a third 103pg channel region, the source electrode S3 of the third transistor T3 can be located in a third 103ps source electrode formation region, and the drain electrode D3 of the third transistor T3 can be located in a third 103pd drain electrode formation region.

[0106] The gate electrode 204g of the fourth transistor T4 can cover a fourth 104pg channel region, the source electrode S4 of the fourth transistor T4 can be located in a fourth channel formation region. Petition 870260037267, dated 04 / 22 / 2026, page 26 / 259 22 / 112 of the 104ps source electrode, and the drain electrode D4 of the fourth transistor T4 may be located in a fourth 104pd drain electrode formation region.

[0107] The gate electrode 205g of the fifth transistor T5 can cover a fifth channel region 105pg, the source electrode S5 of the fifth transistor T5 can be located in a fifth source electrode formation region 105ps, and the drain electrode D5 of the fifth transistor T5 can be located in a fifth drain electrode formation region 105pd.

[0108] The gate electrode 206g of the sixth transistor T6 can cover a sixth 106pg channel region, the source electrode S6 of the sixth transistor T6 can be located in a sixth 106ps source electrode formation region, and the drain electrode D6 of the sixth transistor T6 can be located in a sixth 106pd drain electrode formation region.

[0109] The gate electrode 207g of the seventh transistor T7 can cover a seventh 106pg channel region, the source electrode S7 of the seventh transistor T7 can be located in a seventh 107ps source electrode formation region, and the drain electrode D7 of the seventh transistor T7 can be located in a seventh 107pd drain electrode formation region.

[0110] The gate electrode 203g of the third transistor T3 can be reused as the first electrode plate Cst1 of the storage capacitor Cst, and the second electrode plate Cst2 of the storage capacitor Cst can be coupled in the VDD power line pattern.

[0111] It should be noted that the connection lines 401, 402 and 403 in Figure 1 can be formed by the first metallic source / drain layer, and their arrangement is shown in Figures 3 and 7. The first capacitor C1 in Figure 1 may be a parasitic capacitor. Petition 870260037267, dated 04 / 22 / 2026, page 27 / 259 23 / 112 As shown in Figure 3, an orthogonal projection of the second electrode plate Cst2 of the storage capacitor Cst onto the base can overlap an orthogonal projection of a portion of the fourth drain electrode formation region 104pd that extends downwards onto the base in an overlapping region, i.e., which is formed as the first capacitor C1, the fourth drain electrode formation region 104pd corresponds to the fourth transistor T4.

[0112] Furthermore, in the display substrate according to the embodiments of the present description, the plurality of subpixels may be arranged in a matrix form, that is, in a plurality of rows and columns. Each row of subpixels may include a plurality of subpixels arranged in a second direction, and each column of subpixels may include a plurality of subpixels arranged in a first direction that intersects the second direction. The GATE gate line pattern, the first RST1 reset signal line pattern, the first VINT1 initialization signal line pattern, the EM light emission control signal line pattern, the second RST2 reset signal line pattern, and the second VINT2 initialization signal line pattern of the subpixel may each extend in the second direction, and the DATA data line pattern and the VDD power line pattern of the subpixel may each extend in the first direction.

[0113] The gate line patterns on the same line can be formed entirely as a gate line, the first reset signal line patterns RST1 on the same line can be formed entirely as a first reset signal line, the first initialization signal line patterns VINT1 on the same line can be formed entirely as a first initialization signal line, the signal line patterns of Petition 870260037267, dated 04 / 22 / 2026, page 28 / 259 24 / 112 light emission control EM on the same line can be formed integrally as a light emission control signal line, the second reset signal line patterns RST2 on the same line can be formed integrally as a second reset signal line, the second initialization signal line patterns VINT2 on the same line can be formed integrally as a second initialization signal line, the data line patterns DATA on the same column can be formed integrally as a data line, and the power line patterns VDD on the same column can be formed integrally as a power line.

[0114] In order to simplify a subpixel layout space, the second reset signal line that corresponds to the subpixels in one line can be reused as a first reset signal line that corresponds to the subpixels in a subsequent line. Similarly, the second initialization signal line that corresponds to the subpixels in one line can be reused as the first initialization signal line that corresponds to the subpixels in a subsequent line.

[0115] As shown in Figure 3, in some embodiments, taking the subpixel drive circuit in a subpixel as an example, in the first direction (e.g., a Y direction), the gate electrode 204g of the fourth transistor T4, the gate electrode 201g of the first transistor T1, and the gate electrode 202g of the second transistor T2 may be located on a first side of the gate electrode of the drive transistor (i.e., the gate electrode 203g of the third transistor T3), and the gate electrode of the seventh transistor T7, the gate electrode 206g of the sixth transistor T6, and the gate electrode of the fifth transistor T5 may be located on a second side of the gate electrode of the drive transistor. For example, the first side and the second side of the gate electrode of the drive transistor. Petition 870260037267, dated 04 / 22 / 2026, page 29 / 259 25 / 112 can be two opposite sides of the gate electrode of the drive transistor in the first direction. Furthermore, the first side of the gate electrode of the drive transistor can be the upper side of the gate electrode of the drive transistor, and the second side of the gate electrode of the drive transistor can be the lower side of the gate electrode of the drive transistor T3. For example, the lower side, for example, one side of the display substrate to adhere an Integrated Circuit (IC), can be the lower side of the display substrate, and the side of the gate electrode of the drive transistor closest to the IC can be the lower side of the gate electrode of the drive transistor. The upper side can be the opposite side to the lower side, for example, the side of the gate electrode of the drive transistor furthest from the IC.

[0116] In some embodiments of the present description, as shown in Figure 3, in the second direction (e.g., an X direction), the gate electrode 204g of the fourth transistor T4 and the gate electrode 205g of the fifth transistor T5 may be located on a third side of the gate electrode of the drive transistor, and the gate electrode 201g of the first transistor T1 and the gate electrode 206g of the sixth transistor T6 may be located on a fourth side of the gate electrode of the drive transistor T1. For example, the third side and the fourth side of the gate electrode of the drive transistor may be two opposite sides of the gate electrode of the drive transistor in the second X direction.Furthermore, the third side of the gate electrode of the drive transistor can be a left side of the gate electrode of the drive transistor, and the fourth side of the gate electrode of the drive transistor can be a right side of the gate electrode of the drive transistor. For example, with respect to the left and right sides, in the same subpixel, the first data line pattern DATA1 can be located on the left side of the... Petition 870260037267, dated 04 / 22 / 2026, page 30 / 259 26 / 112 VDD power line pattern, and the VDD power line pattern may be located on the right side of the first DATA1 data line pattern.

[0117] As shown in Figures 3 and 8, the present description provides in some embodiments a display substrate, which includes a base 50 and a plurality of subpixels arranged on the base 50 in a matrix form. The subpixel includes: a data line pattern (e.g., DATA1 in Figure 3) extending in a first direction; a startup signal line pattern (e.g., VINT1 in Figure 3) including a portion extending in a second direction that intersects the first direction, and configured to transmit a startup signal at a fixed potential; and a subpixel drive circuit. The subpixel drive circuit includes a drive transistor (e.g., T3 in Figure 3), a first transistor T1 coupled to a gate electrode of the drive transistor, and a first shield member 404 coupled to the startup signal line pattern.An orthogonal projection of the first shielding member 404 onto base 50 may be located between an orthogonal projection of the first transistor T1 onto base 50 and an orthogonal projection of a target data line pattern (e.g., DATA2 in Figure 3) onto base 50. A next subpixel adjacent to the subpixel in the second direction includes the target data line pattern.

[0118] To be specific, usually the display substrate may include a plurality of subpixels arranged in a matrix form, and each subpixel may include the data line pattern (e.g., DATA1 in Figure 3) extending in the first direction, and the initialization signal line pattern (e.g., VINT1 in Figure 3), at least a portion of which extends in the second direction. The data line pattern is configured to transmit a data signal, and the line pattern Petition 870260037267, dated 04 / 22 / 2026, page 31 / 259 The 27 / 112 startup signal is configured to transmit a startup signal at a fixed potential. For example, the first direction might include the Y direction, and the second direction might include the X direction.

[0119] The target data line pattern can be a data line pattern of a next subpixel adjacent to a current subpixel in the second direction.

[0120] Each subpixel may further include subpixel drive circuits and light-emitting elements that correspond to the subpixel drive circuits respectively. The light-emitting element may include an anode, a layer of organic light-emitting material, and a cathode laminated one upon the other. The anode of the light-emitting element may be coupled to the corresponding subpixel drive circuit, and the light-emitting element may emit light under the control of a drive signal from the subpixel drive circuit.

[0121] More specifically, as shown in Figures 1, 3 and 4, when the subpixel drive circuit includes a 7T1C-based subpixel drive circuit, the gate electrode 203g of the third transistor T3 (i.e., the drive transistor) can be coupled to the drain electrode D1 of the first transistor T1 via a connecting line 401, and the drain electrode D3 of the third transistor T3 can be coupled to the source electrode S1 of the first transistor T1. In the X direction, a minimum straight-line distance between an orthogonal projection of the first 101pg channel region of the first transistor T1 onto base 50 and an orthogonal projection of the target data line pattern (e.g., DATA2 in Figure 3) onto base 50 can be less than a minimum straight-line distance between an orthogonal projection of the third 103pg channel region of the third transistor T3 onto base 50 and the orthogonal projection of the target data line pattern onto base 50.It should be appreciated that the distance in. Petition 870260037267, dated 04 / 22 / 2026, page 32 / 259 28 / 112 minimum straight line between the orthogonal projection of the channel region (e.g., the first channel region 101pg and the third channel region 103pg) onto base 50 and the orthogonal projection of the target data line pattern (e.g., DATA2 in Figure 3) onto base 50 may refer to a minimum distance between an edge of the orthogonal projection of the channel region onto base 50 closest to the target data line pattern and the orthogonal projection of the target data line pattern (e.g., DATA2 in Figure 3) onto base 50.

[0122] In the subpixel drive circuit with the above structure, when a data signal transmitted through the target data line pattern changes, the performance of the first transistor T1 may be affected. Since the first transistor T1 is coupled to the third transistor T3 through the 401 connection line, the operating performance of the third transistor T3 may also be affected.

[0123] According to the embodiments of the present description, the subpixel drive circuit is provided with the first shielding member 404 coupled in the initialization signal line pattern (e.g., VINT1 in Figure 3), so as to provide the first shielding member 404 with the same fixed potential as the initialization signal.Furthermore, the orthogonal projection of the first shielding member 404 onto the base 50 can be located between the orthogonal projection of the first transistor T1 onto the base 50 and the orthogonal projection of the target data line pattern (e.g., DATA2 in Figure 3) onto the base 50, so that this is able to reduce, through the first shielding member 404, the influence caused by the change in the signal transmitted through the target data line pattern on the performance of the first transistor T1, thereby reducing the coupling effect between the gate electrode (i.e., 203g) of the drive transistor and the target data line pattern, reducing vertical crosstalk, and improving the display effect. Petition 870260037267, dated 04 / 22 / 2026, page 33 / 259 29 / 112 of the display substrate during display.

[0124] Furthermore, when the first 404 shielding member is coupled in the initial signal line pattern, this is able to, in addition to providing the first 404 shielding member with the fixed potential, increase a voltage across the initial signal line pattern and provide a more stable voltage for the initial signal transmitted in the initial signal line pattern, thereby improving the operating performance of the subpixel drive circuit.

[0125] It should be appreciated that, in addition to being coupled in the initial signal line pattern, the first 404 shield member can also be coupled in the VDD feed line pattern of the subpixel, so as to allow the first 404 shield member to be at the same fixed potential as the feed transmitted through the VDD feed line pattern.

[0126] As shown in Figure 27, a minimum straight-line distance between the orthogonal projection of the second electrode of the drive transistor (i.e., the drain electrode D3 of the third transistor T3) onto the base and the orthogonal projection of the first shield member 404 onto the base can be L1, a minimum straight-line distance between the orthogonal projection of the second electrode of the drive transistor onto the base and an orthogonal projection of the data line pattern DATA2 of an adjacent subpixel onto the base can be L2.

[0127] One channel length (i.e., the third 103pg channel region) of the drive transistor in the second direction can be L3, and L1 <L2<L3.

[0128] As shown in Figure 28, a minimum straight-line distance between the second electrode of the drive transistor and the data line pattern (e.g., DATA2) of the adjacent subpixel. Petition 870260037267, dated 04 / 22 / 2026, page 34 / 259 30 / 112 could be L4, a minimum straight-line distance between the second electrode of the drive transistor and the first shielding member could be L5, and L5 <L4.

[0129] As shown in Figure 27, a length of a portion of the second electrode of the drive transistor that does not overlap the first shield member 404 in the first direction can be L6, a length of the first shield member 404 in the first direction can be L7, and L6 <L7.

[0130] As shown in Figure 27, an active layer of the first transistor T1 can be arranged in the same layer as, and integrally formed with, an active layer of the drive transistor (i.e., the third transistor T3), so that the active layers can be formed through a single patterning process.

[0131] The second electrode of the drive transistor may be arranged in the same layer as, and integrally formed with, the sixth conductor pattern, and a second shielding member 301 may be arranged between the active layer of the first transistor T1 and the first shielding member 404, such that a minimum straight-line distance between the first shielding member 404 and the second electrode of the drive transistor may be greater than a minimum straight-line distance between the second shielding member 301 and the sixth conductor pattern.

[0132] The first shielding member 404 can be arranged in the same layer as the data line pattern (e.g., DATA2) of the adjacent subpixel, so that these can be formed through a single patterning process. A minimum straight-line distance between a portion of the first shielding member 404 extending in the first direction and the second shielding member 301 can be less than a minimum straight-line distance between the data line pattern of the adjacent subpixel and the Petition 870260037267, dated 04 / 22 / 2026, p. 35 / 259 31 / 112 second armor member 301.

[0133] When the first shielding member 404 is coupled in the VDD power line pattern, although the first shielding member 404 is held at a fixed potential, a parasitic capacitance generated by the VDD power line pattern may increase. At this time, an RC load from the VDD power line pattern may increase, and this is adverse to vertical cross-line relief.

[0134] As shown in Figure 3, in some embodiments of the present description, the gate electrode 201g of the first transistor T1 may be integrally formed with the gate line pattern, and the gate electrode 201g of the first transistor T1 may be a portion of a resulting integral structure capable of forming an overlap region with the active film layer in a direction perpendicular to the base.

[0135] As shown in Figure 3, in some embodiments of the present description, the plurality of subpixels can be arranged in a plurality of lines, and each line of subpixels can include a plurality of subpixels arranged in the second direction. The initialization signal line patterns of the subpixels in the same line can be sequentially coupled to each other to form an initialization signal line that corresponds to the subpixels in the line. The first shielding member 404 can extend in the first direction and can be coupled to at least one initialization signal line.

[0136] To be specific, the plurality of subpixels can be arranged in rows and columns, each row of subpixels can include a plurality of subpixels arranged in a second direction, and each column of subpixels can include a plurality of subpixels arranged in the first direction that intersects the second direction. The patterns of Petition 870260037267, dated 04 / 22 / 2026, p. 36 / 259 32 / 112 initialization signal lines of subpixels on the same line can be sequentially coupled to each other to form an initialization signal line that corresponds to the subpixels on the line.

[0137] When the first shielding member 404 extends in the first direction and is coupled to at least one initialization signal line, it is able for the first shielding member 404 to alleviate the performance of the first transistor T1 from being adversely affected by the change in the signal transmitted through the target data line pattern, thereby reducing the coupling effect between the gate electrode (i.e., 203g) of the drive transistor and the target data line pattern and reducing vertical line crossover, and improving the display effect of the display substrate during display. Furthermore, this is able to increase the voltage across the initialization signal line, and provide a more stable voltage for the initialization signal transmitted through the initialization signal line, thereby improving the operating performance of the subpixel drive circuit.

[0138] As shown in Figure 9, in some embodiments of the present description, the first shielding member 404 can be coupled to two startup signal lines adjacent to it.

[0139] To be specific, when the first 404 shielding member is coupled to the startup signal lines, the first 404 shielding member can be coupled to the startup signal lines in various modes, and the first 404 shielding member can be of various structures and arranged in various modes. For example, as shown in Figure 3, the first 404 shielding member can be coupled to two startup signal lines adjacent to it. In this arrangement mode, the orthogonal projection of the first 404 shielding member onto the base 50 can Petition 870260037267, dated 04 / 22 / 2026, p. 37 / 259 33 / 112 is not only positioned between the orthogonal projection of the first transistor T1 onto base 50 and the orthogonal projection of the target data line pattern onto base 50, but also between an orthogonal projection of the connecting line 401 onto base 50 and the orthogonal projection of the target data line pattern onto base 50, and between an orthogonal projection of the drive transistor (i.e., the third transistor T3) onto base 50 and the orthogonal projection of the target data line pattern onto base 50.

[0140] Through the above arrangement, it is possible to reduce, in a better way, the first crossover line generated between the target signal line pattern and the first transistor T1 and the second crossover line generated between the target signal line pattern and the connection line 401, thereby reducing the indirect crossover line to the drive transistor caused by the first crossover line and the second crossover line. Furthermore, through the above arrangement, it is also possible to further reduce the direct crossover line between the target signal line pattern and the drive transistor, thereby ensuring the operating performance of the display substrate in a better way.

[0141] Referring to Figure 3 again, in some embodiments of the present description, the first shielding pattern 404 may be arranged in a different layer from the initial signal line pattern (e.g., VINT1 in Figure 3), and the orthogonal projection of the first shielding member 404 onto the base 50 may overlap the orthogonal projection of the initial signal line pattern onto the base in a first overlap region, the first shielding member 404 is coupled to the initial signal line pattern through a first via hole arranged in the first overlap region.

[0142] To be specific, the first armor member 404 Petition 870260037267, dated 04 / 22 / 2026, page 38 / 259 34 / 112 can be arranged in the same layer as, or in a different layer from, the initial signal line pattern. When the first shielding member 404 is arranged in a different layer from the initial signal line pattern, the orthogonal projection of the first shielding member 404 onto the base 50 can overlap the orthogonal projection of the initial signal line pattern onto the base 50 in the first overlap region. In this mode, the first shielding member 404 can be coupled to the initial signal line through the first via hole in the first overlap region.

[0143] It should be appreciated that, when the first 404 shielding member is arranged in the same layer as the initial signal line pattern, at least one of the following conditions may exist: the first 404 shielding member and the initial signal line pattern are located in the same horizontal plane, the first 404 shielding member and the initial signal line pattern are located in the same film layer, the first 404 shielding member and the initial signal line pattern are located on a surface of the same insulation layer furthest from the base, and the first 404 shielding member and the initial signal line pattern are formed through a single patterning process.

[0144] When the first 404 shielding member is arranged in a different layer from the initial signal line pattern, at least one of the following conditions may exist: the first 404 shielding member and the initial signal line pattern are not located in the same film layer, and the first 404 shielding member and the initial signal line pattern are incapable of being formed through a single patterning process.

[0145] In some embodiments of the present description, the first Petition 870260037267, dated 04 / 22 / 2026, page 39 / 259 35 / 112 shielding member 404 can be made of the same material as the data line pattern (e.g., DATA1 in Figure 3).

[0146] In some embodiments of the present description, the display substrate may include a first interlayer insulation layer, and the first 404 shielding member and the data line pattern (e.g., DATA1 in Figure 3) may be arranged on a surface of the first interlayer insulation layer furthest from the base.

[0147] To be specific, when the first 404 shielding member is arranged as mentioned above, it is able to simultaneously form the first 404 shielding member and the data line pattern through a single patterning process on the surface of the first interlayer insulation layer furthest from the base, and omit an additional patterning process to form the first 404 shielding member, thereby simplifying the display substrate manufacturing process in a better way, and reducing the manufacturing cost.

[0148] As shown in Figure 3, in some embodiments of the present description, the subpixel drive circuit may further include a second transistor T2 coupled to the gate electrode of the drive transistor. The second transistor T2 may include: a first semiconductor pattern, a second semiconductor pattern, and a third conductor pattern coupled to the first semiconductor pattern and the second semiconductor pattern, the electrical conductivity of the third conductor pattern being greater than the electrical conductivity of the first semiconductor pattern and the electrical conductivity of the second semiconductor pattern; and a first gate electrode pattern and a second gate electrode pattern coupled to each other, an orthogonal projection of the first gate electrode pattern. Petition 870260037267, dated 04 / 22 / 2026, page 40 / 259 36 / 112 on base 50 partially overlapping an orthogonal projection of the first semiconductor pattern on base 50, an orthogonal projection of the second gate electrode pattern on base 50 partially overlapping an orthogonal projection of the second semiconductor pattern on base 50. An orthogonal projection of the third conductor pattern on base 50 may not overlap the orthogonal projection of the first gate electrode pattern on base 50 and the orthogonal projection of the second gate electrode pattern on base 50. The orthogonal projection of the third conductor pattern on base 50 may at least partially overlap the orthogonal projection of the initialization signal line pattern (e.g., VINT1 in Figure 3) on base 50.

[0149] To be specific, as shown in Figure 7, the second transistor T2 may be of a dual-gate structure. The first semiconductor pattern and the second semiconductor pattern of the second transistor may form a channel region (corresponding to a signal location 102pg in Figure 7) of the second transistor T2, and the third conductor pattern 102px of the second transistor may have higher electrical conductivity than the first semiconductor pattern and the second semiconductor pattern due to doping of the third conductor pattern 102px. The first gate electrode pattern and the second gate electrode pattern of the second transistor T2 may cover the first semiconductor pattern and the second semiconductor pattern respectively, and together serve as the gate electrode 202g of the second transistor T2.

[0150] In the second transistor T2 with the above structure, since the third conductor pattern 102px has excellent electrical conductivity and is not covered by the gate electrode pattern, it can be easily coupled to the other neighboring conductor patterns, and through this, a crossover can occur. According to the embodiments of Petition 870260037267, dated 04 / 22 / 2026, page 41 / 259 37 / 112 present description, when the orthogonal projection of the third conductor pattern onto the base 50 at least partially overlaps the orthogonal projection of the initialization signal line pattern (e.g., VINT1 in Figure 3) onto the base 50, it is able for the initialization signal line pattern to shield the third conductor pattern 102px. As the initialization signal at a fixed potential is transmitted on the initialization signal line pattern, this is able to reduce the coupling effect between the third conductor pattern 102px and the other neighboring conductor patterns to a better degree, thereby providing the display substrate with stable operating performance.

[0151] As shown in Figure 4, in some embodiments of the present description, the subpixel drive circuit may further include a first extension member that extends from the first semiconductor pattern and has electrical conductivity superior to the first semiconductor pattern. The first extension member may include a first portion 61, a second portion 62, and a third portion 63. The first portion 61 and the third portion 63 may each extend in the first direction, and the second portion 62 may extend in the second direction. One end of the second portion 62 may be coupled to the first portion 61, the other end of the second portion 62 may be coupled to the third portion 63, and one end of the third portion 63 furthest from the second portion 62 may be coupled to the first transistor T1.

[0152] To be specific, the first extension member and the first semiconductor pattern can be formed through a single patterning process, and after the formation of the first semiconductor pattern, the first extension member can be doped so that the electrical conductivity of the first extension member is higher than that of the first semiconductor pattern.

[0153] After the addition of the first armor member 404, Petition 870260037267, dated 04 / 22 / 2026, page 42 / 259 38 / 112 through the first extension member with the aforementioned structure, this is able to further reduce the influence on the performance of the first transistor T1 and the performance of the second transistor T2 caused by the change in the signal transmitted through the target data line pattern when the second transistor T2 is coupled to the first transistor T1 and the gate electrode of the drive transistor through the first extension member, thereby alleviating a coupling effect between a gate electrode (i.e., 203g) of the drive transistor and the target data line pattern and reducing vertical crosstalk, and improving the display effect of the display substrate during display.

[0154] As shown in Figures 3 and 4, in some embodiments of the present description, the first transistor T1 may include: a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern coupled to the fourth semiconductor pattern and the fifth semiconductor pattern, the electrical conductivity of the sixth conductor pattern being greater than the electrical conductivity of the fourth semiconductor pattern and the electrical conductivity of the fifth semiconductor pattern; and a third gate electrode pattern and a fourth gate electrode pattern coupled to each other.An orthogonal projection of the third gate electrode pattern onto base 50 may partially overlap an orthogonal projection of the fourth semiconductor pattern onto base 50, an orthogonal projection of the fourth gate electrode pattern onto base 50 may partially overlap an orthogonal projection of the fifth semiconductor pattern onto base 50, and an orthogonal projection of the sixth conductor pattern onto base 50 may not overlap the orthogonal projection of the third gate electrode pattern onto base 50 and the orthogonal projection of the fourth gate electrode pattern onto base 50.

[0155] To be specific, as shown in Figure 4, the first Petition 870260037267, dated 04 / 22 / 2026, page 43 / 259 The 39 / 112 transistor may be of a dual-gate structure. The fourth semiconductor pattern and the fifth semiconductor pattern of the first transistor may form a channel region (corresponding to signal 101pg in Figure 4) of the first transistor, and the sixth conductor pattern 101px of the first transistor may have higher electrical conductivity than the fourth semiconductor pattern and the fifth semiconductor pattern due to doping of the sixth conductor pattern 101px. The third electrode pattern and the fourth gate electrode pattern of the first transistor may cover the fourth semiconductor pattern and the fifth semiconductor pattern respectively, and together serve as the gate electrode 201g of the first transistor T1.

[0156] As shown in Figure 10, in some embodiments of the present description, the orthogonal projection of the first shielding member 404 onto the base 50 may at least partially overlap the orthogonal projection of the sixth conductor pattern 101px onto the base 50.

[0157] To be specific, in the first transistor T1 with the above structure, as the sixth conductor pattern 101px has excellent electrical conductivity and is not covered by the gate electrode pattern, it can be easily coupled to the other neighboring conductor patterns, and through this, cross-line can occur. According to the embodiments of the present description, when the orthogonal projection of the first shielding member 404 onto the base 50 at least partially overlaps the orthogonal projection of the sixth conductor pattern 101px onto the base 50, it is able for the first shielding member 404 to shield the sixth conductor pattern 101px. Furthermore, as the first shielding member 404 has a fixed potential, it is able to reduce the coupling effect between the sixth conductor pattern 101px and the other conductor patterns adjacent to the sixth conductor pattern 101px in a better way, for through this Petition 870260037267, dated 04 / 22 / 2026, page 44 / 259 40 / 112 provides the display substrate with more stable operating performance.

[0158] As shown in Figures 11, 12 and 13, in some embodiments of the present description, the subpixel drive circuit may further include a second shielding member 301 coupled to the first shielding member 404, and an orthogonal projection of the second shielding member 301 onto the base 50 may at least partially overlap the orthogonal projection of the sixth conductor pattern 101px onto the base 50.

[0159] To be specific, when the orthogonal projection of the second shielding member 301 onto the base 50 at least partially overlaps the orthogonal projection of the sixth conductor pattern 101px onto the base 50, the second shielding member 301 can shield the sixth conductor pattern 101px. Furthermore, since the second shielding member 301 is coupled to the first shielding member 404, the second shielding member 301 can have a fixed potential, so that this is able to reduce the coupling effect between the sixth conductor pattern 101px and the other conductor patterns adjacent to the sixth conductor pattern 101px in a better way, thereby providing the display substrate with stable operating performance.

[0160] In the display substrate according to the embodiments of the present description, as the first shielding member 404 and the second shielding member 301 each have a fixed potential, this is capable of preventing or reducing parasitic capacitance between the first transistor T1 and the target data line pattern (e.g., DATA2) in a better way, to thereby effectively prevent or reduce vertical crosstalk.

[0161] Furthermore, the orthogonal projection of the second shielding member 301 onto the base 50 can cover the orthogonal projection Petition 870260037267, dated 04 / 22 / 2026, page 45 / 259 41 / 112 whole sixth conductor pattern on base 50.

[0162] To be specific, when the orthogonal projection of the second shielding member 301 onto the base 50 covers the entire orthogonal projection of the sixth conductor pattern 101px onto the base 50, the second shielding pattern 301 can completely shield the sixth conductor pattern 101px, so that this is able to reduce the coupling effect between the sixth conductor pattern 101px and the other conductor patterns adjacent to the sixth conductor pattern 101px to the greatest degree, thereby improving the operating stability of the display substrate in a better way.

[0163] In some embodiments of the present description, the second shielding member 301 and the first shielding member 404 may be arranged in different layers, and the orthogonal projection of the second shielding member 301 onto the base 50 may overlap the orthogonal projection of the first shielding member 404 onto the base 50 in a second overlapping region, the second shielding member 301 is coupled to the first shielding member 404 through a second wayhole arranged in the second overlapping region.

[0164] To be specific, the second shielding member 301 may be arranged in the same layer as, or in a different layer from, the first shielding member 404. When the second shielding member 301 is arranged in a different layer from the first shielding member 404, the orthogonal projection of the second shielding member 301 onto the base 50 may overlap the orthogonal projection of the first shielding member 404 onto the base 50 in the second overlap region. In this mode, the second shielding member 301 may be coupled to the first shielding member 404 through the second wayhole in the second overlap region.

[0165] In some embodiments of the present description, the second Petition 870260037267, dated 04 / 22 / 2026, page 46 / 259 42 / 112 shielding member 301 can be made of the same material as the standard startup signal line.

[0166] In some embodiments of the present description, the display substrate may further include a second interlayer insulation layer, and the second shielding member 301 and the initial signal line pattern (e.g., VINT1 in Figure 3) may be arranged on a surface of the second interlayer insulation layer furthest from the base.

[0167] To be specific, when the second shielding member 301 and the initial signal line pattern are made of the same material, and the second shielding member 301 and the initial signal line pattern (e.g., VINT1 in Figure 3) are arranged on the surface of the second interlayer insulation layer furthest from the base, it is possible to simultaneously form the second shielding member 301 and the initial signal line pattern through a single patterning process, and omit an additional patterning process to form the second shielding member 301, thereby simplifying the display substrate manufacturing process in a better way, and reducing the manufacturing cost.

[0168] As shown in Figure 3, in some embodiments of the present description, the subpixel may further include a VDD power line pattern which includes a portion extending in the first direction. The subpixel drive circuit may further include a storage capacitor Cst, a first electrode plate Cst1 which is reused as the gate electrode of the drive transistor, and a second electrode plate Cst2 which is coupled to the VDD power line pattern and located on the surface of the second interlayer insulation layer furthest from the base.

[0169] To be specific, the storage capacitor Cst of Petition 870260037267, dated 04 / 22 / 2026, page 47 / 259 The 43 / 112 subpixel drive circuit may include the first electrode plate Cst1 and the second electrode plate Cst2 arranged opposite each other. The first electrode plate Cst1 can be coupled to the gate electrode of the drive transistor, and the second electrode plate Cst2 can be coupled to the VDD power line pattern. During the placement of the storage capacitor Cst, the first electrode plate Cst1 can be directly reused as the gate electrode of the drive transistor. In this mode, it is possible not only to ensure that the storage capacitor Cst is coupled to the gate electrode of the drive transistor, but also to reduce the space occupied by the subpixel drive circuit, thereby further improving the resolution of the display substrate.Furthermore, when the second Cst2 electrode plate of the Cst storage capacitor is arranged on the surface of the second interlayer insulation layer furthest from the base, the second Cst2 electrode plate of the Cst storage capacitor can be formed simultaneously through a single patterning with the second shielding member 301 and the initial signal line pattern, so that this is able to simplify the manufacturing process of the display substrate in a better way, and reduce the manufacturing cost.

[0170] As shown in Figure 14, in some embodiments of the present description, the subpixel may further include a reset signal line pattern (e.g., RST1 in Figure 3) extending in the second direction that intersects the first direction. The subpixel drive circuit may further include: a first conductor connecting member 405, an orthogonal projection of which on base 50 at least partially overlaps the orthogonal projection of the sixth conductor pattern 101px on base 50; and a second transistor T2, a first electrode (e.g., a source electrode S2) which is coupled to the initialization signal line pattern (e.g., Petition 870260037267, dated 04 / 22 / 2026, page 48 / 259 44 / 112 VINT1) through the first conductive connection member 405, a second electrode (e.g., a drain electrode D2) is coupled to the gate electrode of the drive transistor, and a gate electrode 202g is coupled to the standard reset signal line (e.g., RST1).

[0171] To be specific, the first conductive connecting member 405 can be made of a metallic material, and formed through a single standardization process with the data line standard.

[0172] When the orthogonal projection of the first 405 conductor connection member onto the base 50 at least partially overlaps the orthogonal projection of the sixth 101px conductor pattern onto the base 50, the first 405 conductor connection member can shield the sixth 101px conductor pattern. Furthermore, since the first 405 conductor connection member is coupled to the initial signal line pattern, the first 405 conductor connection member can have a fixed potential, so that this is able to reduce the coupling effect between the sixth 101px conductor pattern and the other conductor patterns adjacent to the sixth 101px conductor pattern in a better way, thereby providing the display substrate with more stable operating performance.

[0173] As shown in Figure 3, in some embodiments of the present description, the subpixel may further include a GATE gate line pattern, an EM light emission control signal line pattern, a reset signal line pattern (e.g., RST1 in Figure 3), and a VDD power line pattern. The GATE gate line pattern, the EM light emission control signal line pattern, and the reset signal line pattern may extend in the second direction, and the VDD power line pattern may include a portion that extends in the first direction.

[0174] The subpixel drive circuit may also include a Petition 870260037267, dated 04 / 22 / 2026, page 49 / 259 45 / 112 second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. A gate electrode of the drive transistor (e.g., gate electrode 203g of the third transistor T3) can be coupled to the second electrode of the first transistor T1, a first electrode of the drive transistor can be coupled to a second electrode of the fifth transistor T5, and a second electrode of the drive transistor can be coupled to the first electrode of the first transistor T1. Gate electrode 201g of the first transistor T1 can be coupled in the GATE gate line pattern. Gate electrode 202g of the second transistor T2 can be coupled in the reset signal line pattern, a first electrode of the second transistor T2 can be coupled in the initialization signal line pattern, and a second electrode of the second transistor T2 can be coupled to the gate electrode of the drive transistor.A gate electrode 204g from the fourth transistor T4 can be coupled to the GATE gate line pattern, a first electrode from the fourth transistor T4 can be coupled to the data line pattern (e.g., DATA1 in Figure 3), and a second electrode from the fourth transistor T4 can be coupled to the first electrode of the drive transistor. A gate electrode 205g from the fifth transistor T5 can be coupled to the EM light-emitting control signal line pattern, and a first electrode from the fifth transistor T5 can be coupled to the VDD power line pattern. A gate electrode 206g from the sixth transistor T6 can be coupled to the EM light-emitting control signal line pattern, a first electrode from the sixth transistor T6 can be coupled to the second electrode of the drive transistor, and a second electrode from the sixth transistor T6 can be coupled to a subpixel light-emitting element.A 207g gate electrode of the seventh transistor T7 can be coupled to a reset signal line pattern (e.g., RST2) of a nearby subpixel. Petition 870260037267, dated 04 / 22 / 2026, p. 50 / 259 46 / 112 adjacent in the first direction, a first electrode of the seventh transistor T7 can be coupled to a startup signal line pattern (e.g., VINT2) of the next adjacent subpixel, and a second electrode of the seventh transistor T7 can be coupled to the light-emitting element of the subpixel.

[0175] To be specific, in the display substrate above, the plurality of subpixels can be arranged in a matrix form, that is, in rows and columns. Each row of subpixels can include a plurality of subpixels arranged in a second direction, and each column of subpixels can include a plurality of subpixels arranged in the first direction that intersects the second direction.

[0176] It should be noted that the next adjacent subpixel in the first direction may only be a next adjacent subpixel to the seventh transistor in the same column.

[0177] When the subpixel and its subpixel drive circuit have the structures mentioned above, this is able to effectively reduce the layout space occupied by the subpixel drive circuit in order to ensure the operating performance of the subpixel drive circuit, and increase the resolution of the display substrate.

[0178] It should be appreciated that the gate electrode of each transistor in the subpixel drive circuit can be integrally formed with a functional pattern coupled to it. For example, the gate electrode of the first transistor and the gate electrode of the fourth transistor can be integrally formed with their corresponding gate line pattern coupled, the gate electrode of the fifth transistor and the gate electrode of the sixth transistor can be integrally formed with their corresponding light emission control signal line pattern coupled, and the gate electrode of the second transistor and the gate electrode of the seventh transistor can be Petition 870260037267, dated 04 / 22 / 2026, page 51 / 259 47 / 112 formed integrally with the corresponding reset signal line pattern coupled to them.

[0179] In addition, the first transistor T1 is configured to perform threshold compensation on the drive transistor (e.g., the third transistor T3), the second transistor T2 is configured to reset the gate electrode of the drive transistor, the fourth transistor T4 is configured to write a data signal from the data line pattern, the fifth transistor T5 is configured to write power from the power line pattern to the first electrode of the drive transistor, the sixth transistor T6 is configured to control the corresponding light-emitting element to emit light or not, and the seventh transistor T7 is configured to reset the anode of the light-emitting element.

[0180] In some embodiments of the present description, the subpixel may further include a GATE gate line pattern, an EM light emission control signal line pattern, an RST reset signal line pattern, and a VDD power line pattern. Each of the GATE gate line pattern, the EM light emission control signal line pattern, and the RST reset signal line pattern may extend in the second direction, the VDD power line pattern may include a portion extending in the first direction, and the orthogonal projection of the first shielding member 404 onto the base 50 may partially overlap an orthogonal projection of the GATE gate line pattern onto the base 50 and an orthogonal projection of the EM light emission control signal line pattern onto the base 50.

[0181] To be specific, when the first shielding member 404 is arranged as mentioned above, the first shielding member 404 can be used to separate the first transistor T1 and the drive transistor of the target data line pattern (e.g., DATA2), so as to further reduce line crossover. Petition 870260037267, dated 04 / 22 / 2026, page 52 / 259 48 / 112 for the first transistor T1 and the drive transistor caused by the change in the data signal in the target data line pattern.

[0182] In some embodiments of the present description, the second electrode of the seventh transistor T7 can be coupled to the light-emitting element of the subpixel in several ways. For example, an orthogonal projection of the anode of the light-emitting element onto the base can overlap an orthogonal projection of the second electrode of the seventh transistor T7 onto the base in an overlap region, and the anode of the light-emitting element is coupled to the second electrode of the seventh transistor T7 through a via hole disposed in the overlap region. Alternatively, the orthogonal projection of the anode of the light-emitting element onto the base may not overlap the orthogonal projection of the second electrode of the seventh transistor T7 onto the base. The subpixel drive circuit may further include a second conductive connecting member 406 and a third conductive connecting member 407.The orthogonal projection of the anode of the light-emitting element onto the base can overlap an orthogonal projection of a first end of the third conductive connecting member 407 onto the base in an overlapping region; the anode of the light-emitting element is coupled to the first end of the third conductive connecting member 407 through a via hole disposed in the overlapping region. A second end of the third conductive connecting member 407 can overlap a first end of the second conductive connecting member 406. A second end of the third conductive connecting member 407 can be coupled to a first end of the second conductive connecting member 406 through the via hole in the overlapping region. The orthogonal projection of the second electrode of the seventh transistor T7 onto the base can overlap an orthogonal projection of a second end of the second conductive connecting member 406 onto the base. Petition 870260037267, dated 04 / 22 / 2026, page 53 / 259 49 / 112 base in an overlapping region, the second electrode of the seventh transistor T7 is coupled to the second end of the second conductive connecting member 406 through a via hole arranged in the overlapping region. In this mode, the anode of the light-emitting element can be coupled to the second electrode of the seventh transistor T7 through the second conductive connecting member 406 and the third conductive connecting member 407.

[0183] When the anode of the light-emitting element is coupled to the second electrode of the seventh transistor T7 through the second conductive connecting member 406 and the third conductive connecting member 407, the second conductive connecting member 406 may include a portion extending in the first direction. The anode of the light-emitting element may be arranged on an upper side of the light-emitting control signal line pattern of the subpixel corresponding to the light-emitting element, and the second electrode of the seventh transistor T7 may be arranged on a lower side of the light-emitting control signal line pattern of the corresponding subpixel.

[0184] As shown in Figures 15 and 24, the structures of the three-color subpixels will be described hereafter.

[0185] The light-emitting element of a subpixel in a first color may include a first anode 601, a first layer of organic light-emitting material, and a first cathode laminated one on top of the other in the direction away from the base. An orthogonal projection of the first anode 601 onto the base may partially overlap the orthogonal projection of the second electrode of the corresponding seventh transistor T7 onto the base in an overlap region; the first anode 601 is coupled to the second electrode of the corresponding seventh transistor T7 through a via hole disposed in the overlap region.

[0186] The light-emitting element of a subpixel in a Petition 870260037267, dated 04 / 22 / 2026, page 54 / 259 The 50 / 112 second color may include a second anode 602, a second layer of organic light-emitting material, and a second cathode laminated one on top of the other in this order in the direction away from the base. An orthogonal projection of the second anode 602 onto the base may not overlap the orthogonal projection of the second electrode of the corresponding seventh transistor T7 onto the base. The subpixel drive circuit of the subpixel in the second color may further include a second conductive connecting member 406 and a third conductive connecting member 407, and the second anode 602 may be coupled to the second electrode of the corresponding seventh transistor T7 via the second conductive connecting member 406 and the third conductive connecting member 407.

[0187] The light-emitting element of a subpixel in a third color may include a third anode 603, a third layer of organic light-emitting material, and a third cathode laminated one upon the other in this order in the direction away from the base. An orthogonal projection of the third anode 603 onto the base may partially overlap the orthogonal projection of the second electrode of the corresponding seventh transistor T7 onto the base in an overlap region; the third anode 603 is coupled to the second electrode of the corresponding seventh transistor T7 through a via hole disposed in the overlap region.

[0188] For example, as shown in Figure 15, the anode of the organic light-emitting element of the subpixel in each color may include a body electrode and a connecting electrode, and the body electrode may be of a hexagonal shape.

[0189] As shown in Figure 15, the first anode 601 of the subpixel in the first color may include a first body electrode 6011 and a first connecting electrode 6012 which are integrally formed. The first connecting electrode 6012 may be coupled to the second electrode of the seventh transistor T7 of the subpixel in the first color. Petition 870260037267, dated 04 / 22 / 2026, page 55 / 259 51 / 112 through a connecting hole. The second anode 602 of the subpixel in the second color may include a second body electrode 6021 and a second connecting electrode 6022, which are integrally formed. The second connecting electrode 6022 may be coupled to the second electrode of the seventh transistor T7 of the subpixel in the second color through the second conductive connecting member 406 and the third conductive connecting member 407. The third anode 603 of the subpixel in the third color may include a third body electrode 6031 and a third connecting electrode 6032, which are integrally formed. The third connecting electrode 6032 may be connected to the second electrode of the seventh transistor T7 of the subpixel in the third color through a connecting hole.

[0190] For example, the first subpixel connection electrode 6012 in the first color can be arranged on one side of a center of the first body electrode 6011 furthest from the data line pattern of the subpixel drive circuit in the X direction, and on one side of a center of the first body electrode 6011 furthest from the light emission control signal line of the subpixel drive circuit in the Y direction. For example, the first connection electrode 6012 and the first body electrode 6011 of the subpixel in the first color can be arranged in the Y direction, and the first connection electrode 6012 can be located in a lower right corner of the first body electrode 6011.For example, the second subpixel connection electrode 6022 in the second color can be arranged on one side of a center of the second body electrode 6021 furthest from the data line of the subpixel drive circuit in the X direction, and on one side of a center of the second body electrode 6021 closest to the light emission control signal line of the subpixel drive circuit in the Y direction. For example, the second connection electrode 6022 and the second body electrode 6021 of the subpixel in the second color. Petition 870260037267, dated 04 / 22 / 2026, page 56 / 259 52 / 112 can be arranged in the Y direction, and the second connecting electrode 6022 can be located in a lower right corner of the first body electrode 1231. For example, the third connecting electrode 6032 and the third body electrode 6031 of the subpixel in the third color can be arranged in the X direction, and the third connecting electrode 6032 can be arranged on a right side of the third body electrode 6031, that is, on a side of the subpixel drive circuit near the shield line.

[0191] As shown in Figure 15, the first body electrode 6011 of the first anode 601 of the subpixel in the first color may cover the drive transistor of the subpixel in the first color, the second body electrode 6021 of the second anode 602 of the subpixel in the second color may substantially not overlap, or may partially overlap, the drive transistor of the subpixel in the second color, and the third body electrode 6031 of the third anode 603 of the subpixel in the third color may not overlap the drive transistor of the subpixel in the third color.

[0192] As shown in Figure 15, the first body electrode The 601 subpixel in the first color (e.g., a blue subpixel) can overlap the gate line pattern and the light emission control signal line pattern; the second subpixel in the second color (e.g., a red subpixel) can overlap the gate line pattern and the reset signal line pattern; and the third subpixel in the third color (e.g., a green subpixel) can overlap the light emission control signal line pattern, the reset signal line pattern of the subpixel drive circuit in the next line, and the initialization signal line pattern of the subpixel drive circuit in the next line. For example, the third subpixel in the third color (e.g., the green subpixel) can overlap a pixel drive circuit region of a subpixel. Petition 870260037267, dated 04 / 22 / 2026, page 57 / 259 53 / 112 in the first color (for example, a blue subpixel) being adjacent to the subpixel in the third color and on the next line.

[0193] For example, the first body electrode 6011 of the subpixel 601 in the first color may partially overlap the drive transistor of an adjacent subpixel in the third color, and overlap the data line pattern of the subpixel drive circuit of subpixel 601, the first shield member 404, and the data line pattern in the subpixel drive circuit of an adjacent subpixel in the second color. The second body electrode 6021 of the subpixel in the second color may not overlap the data line pattern of the subpixel drive circuit of the subpixel in the second color, but it may overlap the power line pattern of the subpixel drive circuit of the subpixel in the second color, and the power line pattern and data line pattern of the subpixel drive circuit of an adjacent subpixel in the third color.The third 6031 subpixel body electrode in the third color can overlap the data line pattern and the power line pattern of the subpixel drive circuit in the third color, and overlap the power line pattern of the adjacent subpixel drive circuit in the second color.

[0194] For example, as shown in Figure 15, the first connecting electrode 6012 coupled to the first body electrode 6011 of subpixel 601 in the first color can be arranged on one side of the first body electrode 6011 near the reset signal line pattern on a subsequent line, the second connecting electrode 6022 coupled to the second body electrode 6021 of the subpixel in the second color can be arranged on one side of the second body electrode 6021 near the reset signal line pattern on a subsequent line, and the third connecting electrode 6032 connected to the third body electrode 6031 of the subpixel in the third color can be arranged on one side of the Petition 870260037267, dated 04 / 22 / 2026, page 58 / 259 54 / 112 third electrode of body 6031 next to its seventh transistor T7.

[0195] For example, as shown in Figure 15, the first connecting electrode 6012 of subpixel 601 in the first color can overlap the second electrode of the seventh transistor T7 of the subpixel drive circuit of subpixel 601 in the first color. The second connecting electrode 6022 of subpixel in the second color cannot overlap the second electrode of the seventh transistor T7 of the subpixel drive circuit of subpixel in the second color, but the second electrode of the seventh transistor T7 of subpixel in the second color can overlap the third body electrode 6031 of subpixel in the third color. The third connecting electrode 6032 of subpixel in the third color can overlap the second electrode of the seventh transistor T7 of the subpixel drive circuit of subpixel in the third color.

[0196] As shown in Figure 26, the present description further provides in some embodiments a display substrate, which includes a base 50 and a plurality of subpixels arranged on the base 50 in a matrix form.The subpixel includes: a data line pattern (e.g., DATA1) extending in a first direction; a startup signal line pattern (e.g., VINT1) including a portion extending in a second direction that intersects the first direction, the startup signal line pattern being configured to transmit a startup signal at a fixed potential; and a subpixel drive circuit that includes a drive transistor (e.g., a third transistor T3), a first transistor T1 coupled to a gate electrode of the drive transistor, and a first shield member 404 coupled to the startup signal line pattern and configured to form a coupling capacitor with a first electrode (i.e., a source electrode S1) of the first transistor T1. An orthogonal projection of the first shield member 404 onto the base 50 does not overlap. Petition 870260037267, dated 04 / 22 / 2026, page 59 / 259 55 / 112 is an orthogonal projection of a target data line pattern (e.g., DATA2) onto base 50, and the target data line pattern is included in a next subpixel adjacent to the subpixel in the second direction.

[0197] To be specific, usually the display substrate may include a plurality of subpixels arranged in a matrix form, and each subpixel may include a data line pattern (e.g., DATA1 in Figure 3) extending in the first direction, and a startup signal line pattern (e.g., VINT1 in Figure 3), at least a portion of which extends in the second direction. The data line pattern is configured to transmit a data signal, and the startup signal line pattern is configured to transmit a startup signal at a fixed potential. For example, the first direction may include the Y direction, and the second direction may include the X direction.

[0198] The target data line pattern can be a data line pattern of a next subpixel adjacent to a current subpixel in the second direction.

[0199] Each subpixel may further include subpixel drive circuits and light-emitting elements that correspond to the subpixel drive circuits respectively. The light-emitting element may include an anode, a layer of organic light-emitting material, and a cathode laminated one upon the other. The anode of the light-emitting element may be coupled to the corresponding subpixel drive circuit, and the light-emitting element may emit light under the control of a drive signal from the subpixel drive circuit.

[0200] More specifically, as shown in Figures 1, 3 and 4, when the subpixel drive circuit includes a 7T1C-based subpixel drive circuit, the 203g gate electrode Petition 870260037267, dated 04 / 22 / 2026, page 60 / 259The 56 / 112 electrode of the third transistor T3 (i.e., the drive transistor) can be coupled to the drain electrode D1 of the first transistor T1 via a 401 connecting line, and the drain electrode D3 of the third transistor T3 can be coupled to the source electrode S1 of the first transistor T1. In the X direction, a minimum distance between an orthogonal projection of the first 101pg channel region of the first transistor T1 onto base 50 and an orthogonal projection of the target data line pattern (e.g., DATA2 in Figure 3) onto base 50 can be smaller than a minimum distance between an orthogonal projection of the third 103pg channel region of the third transistor T3 onto base 50 and the orthogonal projection of the target data line pattern onto base 50.It should be noted that the minimum distance between the orthogonal projection of the channel region (e.g., the first channel region 101pg and the third channel region 103pg) onto base 50 and the orthogonal projection of the target data line pattern (e.g., DATA2 in Figure 3) onto base 50 may refer to a minimum distance between an edge of the orthogonal projection of the channel region onto base 50 closest to the target data line pattern and the orthogonal projection of the target data line pattern (e.g., DATA2 in Figure 3) onto base 50.

[0201] In the subpixel drive circuit with the above structure, when a data signal transmitted through the target data line pattern changes, the performance of the first transistor T1 may be affected. Since the first transistor T1 is coupled to the third transistor T3 via the connecting line 401, the operating performance of the third transistor T3 may also be affected.

[0202] According to the embodiments of the present description, the subpixel drive circuit is provided with the first shielding member 404 coupled in the initialization signal line pattern (e.g., VINT1 in Figure 3), so as to provide the first shielding member 404 with the same fixed potential as Petition 870260037267, dated 04 / 22 / 2026, page 61 / 259 57 / 112 the initialization signal. Furthermore, the first shielding member 404 can form the coupling capacitor with the first electrode (i.e., the source electrode S1) of the first transistor T1, so that this is able to reduce, through the first shielding member 404, the influence caused by the change in the signal transmitted through the target data line pattern on the performance of the first transistor T1, thereby reducing the coupling effect between the gate electrode (i.e., 203g) of the drive transistor and the target data line pattern and reducing the vertical crossover, and improving the display effect of the display substrate during display.

[0203] Furthermore, when the first shielding member 404 is coupled in the initial signal line pattern, this is able to, in addition to providing the first shielding member 404 with the fixed potential, increase a voltage across the initial signal line pattern and provide a more stable voltage for the initial signal transmitted in the initial signal line pattern, thereby improving the operating performance of the subpixel drive circuit.

[0204] It should be appreciated that, in addition to being coupled in the initial signal line pattern, the first 404 shield member can also be coupled in the VDD feed line pattern of the subpixel, so as to allow the first 404 shield member to be at the same fixed potential as the feed transmitted through the VDD feed line pattern.

[0205] When the first shielding member 404 is coupled to the VDD power line pattern, even though the first shielding member 404 is held at a fixed potential, a parasitic capacitance generated by the VDD power line pattern can increase. During this time, an RC load from the power line pattern of Petition 870260037267, dated 04 / 22 / 2026, page 62 / 259 58 / 112 feeding may increase, and through this it is adverse to the relief of the vertical crossed line.

[0206] As shown in Figure 3, in some embodiments of the present description, the gate electrode 201g of the first transistor T1 can be formed integrally with the gate line pattern, and the gate electrode 201g of the first transistor T1 can be a portion of a resulting integral structure capable of forming an overlap region with the active film layer in a direction perpendicular to the base.

[0207] As shown in Figure 3, in some embodiments of the present description, the plurality of subpixels can be arranged in a plurality of lines, and each line of subpixels can include a plurality of subpixels arranged in a second direction. The initialization signal line patterns of the subpixels in the same line can be sequentially coupled to each other to form an initialization signal line that corresponds to the subpixels in the line. The first shielding member 404 can extend in the first direction and can be coupled to at least one initialization signal line.

[0208] To be specific, the plurality of subpixels can be arranged in rows and columns, each row of subpixels can include a plurality of subpixels arranged in a second direction, and each column of subpixels can include a plurality of subpixels arranged in the first direction that intersects the second direction. The initialization signal line patterns of the subpixels in the same row can be sequentially coupled to each other to form an initialization signal line that corresponds to the subpixels in the row.

[0209] When the first shielding member 404 extends in the first direction and is coupled to at least one signal line of Petition 870260037267, dated 04 / 22 / 2026, p. 63 / 259 The 59 / 112 initialization is capable of alleviating the performance of the first transistor T1 (the first shielding member) from being adversely affected by changes in the signal transmitted through the target data line pattern. This reduces the coupling effect between the gate electrode (i.e., 203g) of the drive transistor and the target data line pattern, reduces vertical line crossover, and improves the display effect of the display substrate during display. Furthermore, it increases the voltage across the initialization signal line and provides a more stable voltage for the initialization signal transmitted through the initialization signal line, thereby improving the operating performance of the subpixel drive circuit.

[0210] As shown in Figure 9, in some embodiments of the present description, the first shielding member 404 can be coupled to two startup signal lines adjacent to it.

[0211] To be specific, when the first shielding member 404 is coupled to the startup signal lines, the first shielding member 404 can be coupled to the startup signal lines in several ways, and the first shielding member 404 can be of several structures and arranged in several ways. For example, as shown in Figure 3, the first shielding member 404 can be coupled to two startup signal lines adjacent to it. In this arrangement mode, the orthogonal projection of the first shielding member 404 onto base 50 can not only be arranged between the orthogonal projection of the first transistor T1 onto base 50 and the orthogonal projection of the target data line pattern onto base 50, but also between an orthogonal projection of the connecting line 401 onto base 50 and the orthogonal projection of the target data line pattern onto base 50, and between an orthogonal projection of the drive transistor (i.e., the third transistor) Petition 870260037267, dated 04 / 22 / 2026, page 64 / 259 60 / 112 transistor T3) on base 50 and the orthogonal projection of the target data line pattern onto base 50.

[0212] Through the above arrangement, it is possible to reduce, in a better way, the first crossover line generated between the target signal line pattern and the first transistor T1 and the second crossover line generated between the target signal line pattern and the connection line 401, thereby reducing the indirect crossover line to the drive transistor caused by the first crossover line and the second crossover line. Furthermore, through the above arrangement, it is also possible to further reduce the direct crossover line between a target signal line pattern and the drive transistor, thereby ensuring the operating performance of the display substrate in a better way.

[0213] Referring to Figure 3 again, in some embodiments of the present description, the first shielding pattern 404 may be arranged in a different layer from the initial signal line pattern (e.g., VINT1 in Figure 3), and the orthogonal projection of the first shielding member 404 onto the base 50 may overlap the orthogonal projection of the initial signal line pattern onto the base in a first overlap region, the first shielding member 404 is coupled to the initial signal line pattern through a first via hole arranged in the first overlap region.

[0214] To be specific, the first 404 shielding member can be arranged in the same layer as, or in a different layer from, the initial signal line pattern. When the first 404 shielding member is arranged in a different layer from the initial signal line pattern, the orthogonal projection of the first 404 shielding member onto the base 50 can overlap the orthogonal projection of the signal line pattern. Petition 870260037267, dated 04 / 22 / 2026, page 65 / 259 61 / 112 initialization on base 50 in the first overlap region. In this mode, the first shielding member 404 can be coupled to the initialization signal line through the first via hole in the first overlap region.

[0215] It should be appreciated that, when the first 404 shielding member is arranged in the same layer as the initial signal line pattern, at least one of the following conditions may exist: the first 404 shielding member and the initial signal line pattern are located in the same horizontal plane, the first 404 shielding member and the initial signal line pattern are located in the same film layer, the first 404 shielding member and the initial signal line pattern are located on a surface of the same insulation layer furthest from the base, and the first 404 shielding member and the initial signal line pattern are formed through a single patterning process.

[0216] When the first 404 shielding member is arranged in a different layer from the initial signal line pattern, at least one of the following conditions may exist: the first 404 shielding member and the initial signal line pattern are not located in the same film layer, and the first 404 shielding member and the initial signal line pattern are incapable of being formed through a single patterning process.

[0217] In some embodiments of the present description, the first shielding member 404 may be made of the same material as the data line pattern (e.g., DATA1 in Figure 3).

[0218] In some embodiments of the present description, the display substrate may include a first interlayer insulation layer, and the first 404 shielding member and the data line pattern (e.g., DATA1 in Figure 3) may be arranged in Petition 870260037267, dated 04 / 22 / 2026, p. 66 / 259 62 / 112 a surface of the first interlayer insulation layer furthest from the base.

[0219] To be specific, when the first 404 shielding member is arranged as mentioned above, it is able to simultaneously form the first 404 shielding member and the data line pattern through a single patterning process on the surface of the first interlayer insulation layer furthest from the base, and omit an additional patterning process to form the first 404 shielding member, thereby simplifying the display substrate manufacturing process in a better way, and reducing the manufacturing cost.

[0220] As shown in Figure 3, in some embodiments of the present description, the subpixel drive circuit may also include a second transistor T2 coupled to the gate electrode of the drive transistor.The second transistor T2 may include: a first semiconductor pattern, a second semiconductor pattern, and a third conductor pattern coupled to the first semiconductor pattern and the second semiconductor pattern, the electrical conductivity of the third conductor pattern being greater than the electrical conductivity of the first semiconductor pattern and the electrical conductivity of the second semiconductor pattern; and a first gate electrode pattern and a second gate electrode pattern coupled to each other, an orthogonal projection of the first gate electrode pattern onto the base 50 partially overlapping an orthogonal projection of the first semiconductor pattern onto the base 50, an orthogonal projection of the second gate electrode pattern onto the base 50 partially overlapping an orthogonal projection of the second semiconductor pattern onto the base 50. An orthogonal projection of the third conductor pattern onto the base 50 may not overlap the projection. Petition 870260037267, dated 04 / 22 / 2026, page 67 / 259 63 / 112 orthogonal projection of the first gate electrode pattern onto base 50 and the orthogonal projection of the second gate electrode pattern onto base 50. The orthogonal projection of the third conductor pattern onto base 50 may at least partially overlap the orthogonal projection of the initial signal line pattern (e.g., VINT1 in Figure 3) onto base 50.

[0221] To be specific, as shown in Figure 7, the second transistor T2 may be of a dual-gate structure. The first semiconductor pattern and the second semiconductor pattern of the second transistor may form a channel region (corresponding to a signal location 102pg in Figure 7) of the second transistor T2, and the third conductor pattern 102px of the second transistor may have higher electrical conductivity than the first semiconductor pattern and the second semiconductor pattern due to doping. The first gate electrode pattern and the second gate electrode pattern of the second transistor T2 may cover the first semiconductor pattern and the second semiconductor pattern respectively, and together serve as the gate electrode 202g of the second transistor T2.

[0222] In the second transistor T2 with the above structure, since the third conductor pattern 102px has excellent electrical conductivity and is not covered by the gate electrode pattern, it can be easily coupled to the other neighboring conductor patterns, and through this, line crossing can occur. According to the embodiments of the present description, when the orthogonal projection of the third conductor pattern onto the base 50 at least partially overlaps the orthogonal projection of the startup signal line pattern (e.g., VINT1 in Figure 3) onto the base 50, it is able for the startup signal line pattern to shield the third conductor pattern 102px. Since the startup signal at a fixed potential is transmitted in the startup signal line pattern, Petition 870260037267, dated 04 / 22 / 2026, page 68 / 259 64 / 112 is capable of reducing the coupling effect between the third 102px driver pattern and the other neighboring driver patterns in a better way, thereby providing the display substrate with stable operating performance.

[0223] As shown in Figure 4, in some embodiments of the present description, the subpixel drive circuit may further include a first extension member that extends from the first semiconductor pattern and has an electrical conductivity higher than the first semiconductor pattern. The first extension member may include a first portion 61, a second portion 62, and a third portion 63. The first portion 61 and the third portion 63 may each extend in the first direction, and the second portion 62 may extend in the second direction. One end of the second portion 62 may be coupled to the first portion 61, the other end of the second portion 62 may be coupled to the third portion 63, and one end of the third portion 63 furthest from the second portion 62 may be coupled to the first transistor T1.

[0224] To be specific, the first extension member and the first semiconductor pattern can be formed through a single patterning process, and after the formation of the first semiconductor pattern, the first extension member can be doped so that the electrical conductivity of the first extension member is higher than that of the first semiconductor pattern.

[0225] After adding the first shielding member 404, through the first extension member with the aforementioned structure, this is able to further reduce the influence on the performance of the first transistor T1 and the performance of the second transistor T2 caused by the change in the signal transmitted through the target data line pattern when the second transistor T2 is coupled to the first transistor T1 and the gate electrode of the transistor. Petition 870260037267, dated 04 / 22 / 2026, page 69 / 259 65 / 112 drive via the first extension member, thereby alleviating a coupling effect between the gate electrode (i.e., 203g) of the drive transistor and the target data line pattern and reducing the vertical crosshair, and improving the display effect of the display substrate during display.

[0226] As shown in Figures 3 and 4, in some embodiments of the present description, the first transistor T1 may include: a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern coupled to the fourth semiconductor pattern and the fifth semiconductor pattern, the electrical conductivity of the sixth conductor pattern being greater than the electrical conductivity of the fourth semiconductor pattern and the electrical conductivity of the fifth semiconductor pattern; and a third gate electrode pattern and a fourth gate electrode pattern coupled to each other.An orthogonal projection of the third gate electrode pattern onto base 50 may partially overlap an orthogonal projection of the fourth semiconductor pattern onto base 50, an orthogonal projection of the fourth gate electrode pattern onto base 50 may partially overlap an orthogonal projection of the fifth semiconductor pattern onto base 50, and an orthogonal projection of the sixth conductor pattern onto base 50 may not overlap the orthogonal projection of the third gate electrode pattern onto base 50 and the orthogonal projection of the fourth gate electrode pattern onto base 50.

[0227] To be specific, as shown in Figure 4, the first transistor may be of a double-gate structure. The fourth semiconductor pattern and the fifth semiconductor pattern of the first transistor may form a channel region (corresponding to signal 101pg in Figure 4) of the first transistor, and the sixth conductor pattern 101px of the first transistor may have higher electrical conductivity than the fourth semiconductor pattern and the fifth semiconductor pattern. Petition 870260037267, dated 04 / 22 / 2026, p. 70 / 259 66 / 112 due to doping. The third electrode pattern and the fourth gate electrode pattern of the first transistor can cover the fourth semiconductor pattern and the fifth semiconductor pattern respectively, and together serve as the 201g gate electrode of the first transistor T1.

[0228] As shown in Figure 10, in some embodiments of the present description, the orthogonal projection of the first shielding member 404 onto the base 50 may at least partially overlap the orthogonal projection of the sixth conductor pattern 101px onto the base 50.

[0229] To be specific, in the first transistor T1 with the above structure, as the sixth conductor pattern 101px has excellent electrical conductivity and is not covered by the gate electrode pattern, it can be easily coupled to the other neighboring conductor patterns, and through this the cross-line can occur. According to the embodiments of the present description, when the orthogonal projection of the first shielding member 404 onto the base 50 at least partially overlaps the orthogonal projection of the sixth conductor pattern 101px onto the base 50, it is capable for the first shielding member 404 to shield the sixth conductor pattern 101px.Furthermore, since the first 404 shielding member has a fixed potential, it is able to reduce the coupling effect between the sixth 101px conductor pattern and the other conductor patterns adjacent to the sixth 101px conductor pattern to a better degree, thereby providing the display substrate with more stable operating performance.

[0230] As shown in Figures 11, 12 and 13, in some embodiments of the present description, the subpixel drive circuit may also include a second shielding member 301 coupled to the first shielding member 404, and an orthogonal projection of the second shielding member 301 onto the base 50 may Petition 870260037267, dated 04 / 22 / 2026, page 71 / 259 67 / 112 at least partially overlap the orthogonal projection of the sixth conductor pattern 101 px onto the base 50.

[0231] To be specific, when the orthogonal projection of the second shielding member 301 onto the base 50 at least partially overlaps the orthogonal projection of the sixth conductor pattern 101px onto the base 50, the second shielding member 301 can shield the sixth conductor pattern 101px. Furthermore, since the second shielding member 301 is coupled to the first shielding member 404, the second shielding member 301 can have a fixed potential, so that this is able to reduce the coupling effect between the sixth conductor pattern 101px and the other conductor patterns adjacent to the sixth conductor pattern 101px in a better way, thereby providing the display substrate with stable operating performance.

[0232] In the display substrate according to the embodiments of the present description, as the first shielding member 404 and the second shielding member 303 each have a fixed potential, this is capable of preventing or reducing parasitic capacitance between the first transistor T1 and the target data line pattern (e.g., DATA2) in a better way, to thereby effectively prevent or reduce vertical crosstalk.

[0233] Furthermore, the orthogonal projection of the second shielding member 301 onto the base 50 can cover the entire orthogonal projection of the sixth conductor pattern onto the base 50.

[0234] To be specific, when the orthogonal projection of the second shielding member 301 onto the base 50 covers the entire orthogonal projection of the sixth conductor pattern 101px onto the base 50, the second shielding pattern 301 can completely shield the sixth conductor pattern 101px, so that this is able to reduce the coupling effect between the sixth conductor pattern 101px and the Petition 870260037267, dated 04 / 22 / 2026, page 72 / 259 68 / 112 other conductor patterns adjacent to the sixth conductor pattern 101px to the greatest extent, in order to thereby improve the operating stability of the display substrate in a better way.

[0235] In some embodiments of the present description, the second shielding member 301 and the first shielding member 404 may be arranged in different layers, and the orthogonal projection of the second shielding member 301 onto the base 50 may overlap the orthogonal projection of the first shielding member 404 onto the base 50 in a second overlapping region, the second shielding member 301 is coupled to the first shielding member 404 through a second wayhole arranged in the second overlapping region.

[0236] To be specific, the second shielding member 301 can be arranged in the same layer as, or in a different layer from, the first shielding member 404. When the second shielding member 301 is arranged in a different layer from the first shielding member 404, the orthogonal projection of the second shielding member 301 onto the base 50 can overlap the orthogonal projection of the first shielding member 404 onto the base 50 in the second overlap region. In this mode, the second shielding member 301 can be coupled to the first shielding member 404 through the second wayhole in the second overlap region.

[0237] In some embodiments of the present description, the second shielding member 301 may be made of the same material as the initial signal line pattern.

[0238] In some embodiments of the present description, the display substrate may further include a second interlayer insulation layer, and the second shielding member 301 and the initialization signal line pattern (e.g., VINT1 in Figure 3) may Petition 870260037267, dated 04 / 22 / 2026, page 73 / 259 69 / 112 are arranged on a surface of the second interlayer insulation layer furthest from the base.

[0239] To be specific, when the second shielding member 301 and the initial signal line pattern are made of the same material, and the second shielding member 301 and the initial signal line pattern (e.g., VINT1 in Figure 3) are arranged on the surface of the second interlayer insulation layer furthest from the base, it is possible to simultaneously form the second shielding member 301 and the initial signal line pattern through a single patterning process, and omit an additional patterning process to form the second shielding member 301, thereby simplifying the display substrate manufacturing process in a better way, and reducing the manufacturing cost.

[0240] As shown in Figure 3, in some embodiments of the present description, the subpixel may further include a VDD power line pattern which includes a portion extending in the first direction. The subpixel drive circuit may further include a storage capacitor Cst, a first electrode plate Cst1 which is reused as a gate electrode of the drive transistor, and a second electrode plate Cst2 which is coupled to the VDD power line pattern and located on the surface of the second interlayer insulation layer furthest from the base.

[0241] To be specific, the storage capacitor Cst of the subpixel drive circuit may include the first electrode plate Cst1 and the second electrode plate Cst2 arranged opposite each other. The first electrode plate Cst1 may be coupled to the gate electrode of the drive transistor, and the second electrode plate Cst2 may be coupled to the VDD power line pattern. During the arrangement of the storage capacitor Cst, the Petition 870260037267, dated 04 / 22 / 2026, page 74 / 259 The first electrode plate Cst1 (70 / 112) can be directly reused as the gate electrode of the drive transistor. In this way, it not only ensures that the storage capacitor Cst is coupled to the gate electrode of the drive transistor, but also reduces the space occupied by the subpixel drive circuit, thereby further improving the resolution of the display substrate. Furthermore, when the second electrode plate Cst2 of the storage capacitor Cst is placed on the surface of the second interlayer insulation layer furthest from the base, the second electrode plate Cst2 of the storage capacitor Cst can be simultaneously formed through a single pattern with the second shield member 301 and the initial signal line pattern, thus simplifying the manufacturing process of the display substrate and reducing manufacturing costs.

[0242] As shown in Figure 14, in some embodiments of the present description, the subpixel may also include a reset signal line pattern (e.g., RST1 in Figure 3) that extends in a second direction intersecting the first direction. The subpixel drive circuit may also include: a first conductor connection member 405, an orthogonal projection of which onto base 50 at least partially overlaps the orthogonal projection of the sixth conductor pattern 101px onto base 50; and a second transistor T2, a first electrode (e.g., a source electrode S2) of which is coupled to the startup signal line pattern (e.g., VINT1) via the first conductor connection member 405, a second electrode (e.g., a drain electrode D2) of which is coupled to the gate electrode of the drive transistor, and a gate electrode 202g of which is Petition 870260037267, dated 04 / 22 / 2026, page 75 / 259 71 / 112 coupled in the reset signal line pattern (e.g., RST1).

[0243] To be specific, the first conductive connecting member 405 can be made of a metallic material, and formed through a single standardization process with the data line standard.

[0244] When the orthogonal projection of the first 405 conductor connection member onto the base 50 at least partially overlaps the orthogonal projection of the sixth 101px conductor pattern onto the base 50, the first 405 conductor connection member can shield the sixth 101px conductor pattern. Furthermore, since the first 405 conductor connection member is coupled to the initial signal line pattern, the first 405 conductor connection member can have a fixed potential, so that this is able to reduce the coupling effect between the sixth 101px conductor pattern and the other conductor patterns adjacent to the sixth 101px conductor pattern in a better way, thereby providing the display substrate with more stable operating performance.

[0245] As shown in Figure 3, in some embodiments of the present description, the subpixel may further include a GATE gate line pattern, an EM light emission control signal line pattern, a reset signal line pattern (e.g., RST1 in Figure 3), and a VDD power line pattern. The GATE gate line pattern, the EM light emission control signal line pattern, and the reset signal line pattern may extend in the second direction, and the VDD power line pattern may include a portion that extends in the first direction.

[0246] The subpixel drive circuit may also include a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. A gate electrode of the drive transistor (e.g., the 203g gate electrode of the third transistor T3) may be coupled to the second electrode of the Petition 870260037267, dated 04 / 22 / 2026, page 76 / 25972 / 112 first transistor T1, a first electrode of the drive transistor can be coupled to a second electrode of the fifth transistor T5, and a second electrode of the drive transistor can be coupled to the first electrode of the first transistor T1. The gate electrode 201g of the first transistor T1 can be coupled in the gate line pattern. A gate electrode 202g of the second transistor T2 can be coupled in the reset signal line pattern, a first electrode of the second transistor T2 can be coupled in the initialization signal line pattern, and a second electrode of the second transistor T2 can be coupled to the gate electrode of the drive transistor.A gate electrode 204g from the fourth transistor T4 can be coupled to the GATE gate line pattern, a first electrode from the fourth transistor T4 can be coupled to the data line pattern (e.g., DATA1 in Figure 3), and a second electrode from the fourth transistor T4 can be coupled to the first electrode of the drive transistor. A gate electrode 205g from the fifth transistor T5 can be coupled to the EM light-emitting control signal line pattern, and a first electrode from the fifth transistor T5 can be coupled to the VDD power line pattern. A gate electrode 206g from the sixth transistor T6 can be coupled to the EM light-emitting control signal line pattern, a first electrode from the sixth transistor T6 can be coupled to the second electrode of the drive transistor, and a second electrode from the sixth transistor T6 can be coupled to a subpixel light-emitting element.A gate electrode 207g of the seventh transistor T7 can be coupled to a reset signal line pattern (e.g., RST2) of a next adjacent subpixel in the first direction, a first electrode of the seventh transistor T7 can be coupled to a start signal line pattern (e.g., VINT2) of the next adjacent subpixel, and a second electrode of the seventh transistor T7 can be coupled to the emitting element of. Petition 870260037267, dated 04 / 22 / 2026, p. 77 / 259 73 / 112 subpixel light.

[0247] To be specific, in the display substrate above, the plurality of subpixels can be arranged in a matrix form, that is, in rows and columns. Each row of subpixels can include a plurality of subpixels arranged in the second direction, and each column of subpixels can include a plurality of subpixels arranged in the first direction that intersects the second direction.

[0248] It should be noted that the next adjacent subpixel in the first direction can only be a next adjacent subpixel to the seventh transistor in the same column.

[0249] When the subpixel and its subpixel drive circuit have the structures mentioned above, this is able to effectively reduce the layout space occupied by the subpixel drive circuit in order to ensure the operating performance of the subpixel drive circuit, and increase the resolution of the display substrate.

[0250] It should be appreciated that the gate electrode of each transistor in the subpixel drive circuit can be integrally formed with a functional pattern coupled to it. For example, the gate electrode of the first transistor and the gate electrode of the fourth transistor can be integrally formed with their corresponding gate line pattern coupled, the gate electrode of the fifth transistor and the gate electrode of the sixth transistor can be integrally formed with their corresponding light emission control signal line pattern coupled, and the gate electrode of the second transistor and the gate electrode of the seventh transistor can be integrally formed with the corresponding reset signal line pattern coupled to them.

[0251] In addition, the first transistor T1 is configured to perform threshold compensation on the drive transistor (by Petition 870260037267, dated 04 / 22 / 2026, page 78 / 259 74 / 112 example, the third transistor T3), the second transistor T2 is configured to reset the gate electrode of the drive transistor, the fourth transistor T4 is configured to write a data signal of the data line pattern, the fifth transistor T5 is configured to write power of the power line pattern to the first electrode of the drive transistor, the sixth transistor T6 is configured to control the corresponding light-emitting element to emit light or not, and the seventh transistor T7 is configured to reset the anode of the light-emitting element.

[0252] In some embodiments of the present description, the subpixel may further include a GATE gate line pattern, an EM light-emitting control signal line pattern, an RST reset signal line pattern, and a VDD power line pattern.Each of the GATE gate line pattern, the EM light emission control signal line pattern, and the RST reset signal line pattern can extend in the second direction, the VDD power line pattern can include a portion that extends in the first direction, and the orthogonal projection of the first shielding member 404 onto base 50 can partially overlap an orthogonal projection of the GATE gate line pattern onto base 50 and an orthogonal projection of the EM light emission control signal line pattern onto base 50.

[0253] To be specific, when the first shielding member 404 is arranged as mentioned above, the first shielding member 404 can be used to separate the first transistor T1 and the drive transistor from the target data line pattern (e.g., DATA2), so as to further reduce line crossover to the first transistor T1 and the drive transistor caused by the change in the data signal in the target data line pattern.

[0254] In some embodiments of the present description, the second Petition 870260037267, dated 04 / 22 / 2026, p. 79 / 259 The 75 / 112 electrode of the seventh transistor T7 can be coupled to the light-emitting element of the subpixel in several ways. For example, an orthogonal projection of the anode of the light-emitting element onto the base can overlap an orthogonal projection of the second electrode of the seventh transistor T7 onto the base in an overlap region, and the anode of the light-emitting element is coupled to the second electrode of the seventh transistor T7 through a via hole disposed in the overlap region. Alternatively, the orthogonal projection of the anode of the light-emitting element onto the base may not overlap the orthogonal projection of the second electrode of the seventh transistor T7 onto the base. The subpixel drive circuit may further include a second conductive connecting member 406 and a third conductive connecting member 407.The orthogonal projection of the anode of the light-emitting element onto the base may overlap an orthogonal projection of a first end of the third conductor connecting member 407 onto the base in an overlapping region; the anode of the light-emitting element is coupled to the first end of the third conductor connecting member 407 through a way hole disposed in the overlapping region. A second end of the third conductor connecting member 407 may overlap a first end of the second conductor connecting member 406. A second end of the third conductor connecting member 407 may be coupled to a first end of the second conductor connecting member 406 through the way hole in the overlapping region.The orthogonal projection of the second electrode of the seventh transistor T7 onto the base can overlap an orthogonal projection of a second end of the second conductive connecting member 406 onto the base in an overlapping region; the second electrode of the seventh transistor T7 is coupled to the second end of the second conductive connecting member 406 through a provided via hole. Petition 870260037267, dated 04 / 22 / 2026, page 80 / 259 76 / 112 in the overlap region. In this mode, the anode of the light-emitting element can be coupled to the second electrode of the seventh transistor T7 through the second conductive connection member 406 and the third conductive connection member 407.

[0255] When the anode of the light-emitting element is coupled to the second electrode of the seventh transistor T7 through the second conductive connecting member 406 and the third conductive connecting member 407, the second conductive connecting member 406 may include a portion extending in the first direction. The anode of the light-emitting element may be arranged on an upper side of the light-emitting control signal line pattern of the subpixel corresponding to the light-emitting element, and the second electrode of the seventh transistor T7 may be arranged on a lower side of the light-emitting control signal line pattern of the corresponding subpixel.

[0256] As shown in Figure 15, the structures of the three-color subpixels will be described hereafter as an example.

[0257] The light-emitting element of a subpixel in a first color may include a first anode 601, a first layer of organic light-emitting material, and a first cathode laminated one on top of the other in this order in the direction away from the base. An orthogonal projection of the first anode 601 onto the base may partially overlap the orthogonal projection of the second electrode of the corresponding seventh transistor T7 onto the base in an overlap region; the first anode 601 is coupled to the second electrode of the corresponding seventh transistor T7 through a via hole disposed in the overlap region.

[0258] The light-emitting element of a subpixel in a second color may include a second anode 602, a second layer of organic light-emitting material, and a second cathode. Petition 870260037267, dated 04 / 22 / 2026, page 81 / 259 77 / 112 laminates stacked on top of each other in this order in the direction away from the base. An orthogonal projection of the second anode 602 onto the base may not overlap the orthogonal projection of the second electrode of the corresponding seventh transistor T7 onto the base. The subpixel drive circuit for the second color subpixel may also include a second conductive connecting member 406 and a third conductive connecting member 407, and the second anode 602 may be coupled to the second electrode of the corresponding seventh transistor T7 via the second conductive connecting member 406 and the third conductive connecting member 407.

[0259] The light-emitting element of a subpixel in a third color may include a third anode 603, a third layer of organic light-emitting material, and a third cathode laminated one upon the other in this order in the direction away from the base. An orthogonal projection of the third anode 603 onto the base may partially overlap the orthogonal projection of the second electrode of the corresponding seventh transistor T7 onto the base in an overlap region; the third anode 603 is coupled to the second electrode of the corresponding seventh transistor T7 through a via hole disposed in the overlap region.

[0260] For example, as shown in Figure 15, the anode of the organic light-emitting element of the subpixel in each color may include a body electrode and a connecting electrode, and the body electrode may be of a hexagonal shape.

[0261] As shown in Figure 15, the first anode 601 of the subpixel in the first color may include a first body electrode 6011 and a first connecting electrode 6012 which are integrally formed. The first connecting electrode 6012 may be coupled to the second electrode of the seventh transistor T7 of the subpixel in the first color through a connecting hole. The second anode 602 of the subpixel in Petition 870260037267, dated 04 / 22 / 2026, page 82 / 259 The second color subpixel (78 / 112) may include a second body electrode 6021 and a second connecting electrode 6022, which are integrally formed. The second connecting electrode 6022 may be coupled to the second electrode of the seventh transistor T7 of the second color subpixel via the second conductive connecting member 406 and the third conductive connecting member 407. The third anode 603 of the third color subpixel may include a third body electrode 6031 and a third connecting electrode 6032, which are integrally formed. The third connecting electrode 6032 may be connected to the second electrode of the seventh transistor T7 of the third color subpixel via a connecting hole.

[0262] For example, the first subpixel connection electrode 6012 in the first color can be arranged on one side of a center of the first body electrode 6011 furthest from the data line pattern of the subpixel drive circuit in the X direction, and on one side of a center of the first body electrode 6011 furthest from the light emission control signal line of the subpixel drive circuit in the Y direction. For example, the first connection electrode 6012 and the first body electrode 6011 of the subpixel in the first color can be arranged in the Y direction, and the first connection electrode 6012 can be located in a lower right corner of the first body electrode 6011.For example, the second subpixel connection electrode 6022 in the second color can be arranged on one side of a center of the second body electrode 6021 furthest from the data line of the subpixel drive circuit in the X direction, and on one side of a center of the second body electrode 6021 closest to the light emission control signal line of the subpixel drive circuit in the Y direction. For example, the second connection electrode 6022 and the second body electrode 6021 of the subpixel in the second color can be arranged in the Y direction, and the second connection electrode... Petition 870260037267, dated 04 / 22 / 2026, page 83 / 259 79 / 112 6022 may be located in a lower right corner of the first body electrode 1231. For example, the third connecting electrode 6032 and the third body electrode 6031 of the subpixel in the third color may be arranged in the X direction, and the third connecting electrode 6032 may be arranged on a right side of the third body electrode 6031, that is, on a side of the subpixel drive circuit close to the shield line.

[0263] As shown in Figure 15, the first body electrode 6011 of the first anode 601 of the subpixel in the first color may cover the drive transistor of the subpixel in the first color, the second body electrode 6021 of the second anode 602 of the subpixel in the second color may substantially not overlap, or may partially overlap, the drive transistor of the subpixel in the second color, and the third body electrode 6031 of the third anode 603 of the subpixel in the third color may not overlap the drive transistor of the subpixel in the third color.

[0264] As shown in Figure 15, the first body electrode The 601 subpixel in the first color (e.g., a blue subpixel) can overlap the gate line pattern and the light emission control signal line pattern; the second subpixel in the second color (e.g., a red subpixel) can overlap the gate line pattern and the reset signal line pattern; and the third subpixel in the third color (e.g., a green subpixel) can overlap the light emission control signal line pattern, the reset signal line pattern of the subpixel drive circuit in the next line, and the initialization signal line pattern of the subpixel drive circuit in the next line. For example, the third subpixel in the third color (e.g., the green subpixel) can overlap a pixel drive circuit region of a subpixel. Petition 870260037267, dated 04 / 22 / 2026, page 84 / 259 80 / 112 in the first color (for example, a blue subpixel) being adjacent to the subpixel in the third color and on the next line.

[0265] For example, the first body electrode 6011 of the subpixel 601 in the first color may partially overlap the drive transistor of an adjacent subpixel in the third color, and overlap the data line pattern of the subpixel drive circuit of subpixel 601, the first shield member 404, and the data line pattern in the subpixel drive circuit of an adjacent subpixel in the second color. The second body electrode 6021 of the subpixel in the second color may not overlap the data line pattern of the subpixel drive circuit of the subpixel in the second color, but it may overlap the power line pattern of the subpixel drive circuit of the subpixel in the second color, and the power line pattern and data line pattern of the subpixel drive circuit of an adjacent subpixel in the third color.The third 6031 subpixel body electrode in the third color can overlap the data line pattern and the power line pattern of the subpixel drive circuit in the third color, and overlap the power line pattern of the adjacent subpixel drive circuit in the second color.

[0266] For example, as shown in Figure 15, the first connecting electrode 6012 coupled to the first body electrode 6011 of subpixel 601 in the first color can be arranged on one side of the first body electrode 6011 near the reset signal line pattern on a subsequent line, the second connecting electrode 6022 coupled to the second body electrode 6021 of the subpixel in the second color can be arranged on one side of the second body electrode 6021 near the reset signal line pattern on a subsequent line, and the third connecting electrode 6032 connected to the third body electrode 6031 of the subpixel in the third color can be arranged on one side of the third body electrode 6031 near the Petition 870260037267, dated 04 / 22 / 2026, page 85 / 259 81 / 112 your seventh transistor T7.

[0267] For example, as shown in Figure 15, the first connecting electrode 6012 of subpixel 601 in the first color can overlap the second electrode of the seventh transistor T7 of the subpixel drive circuit of subpixel 601 in the first color. The second connecting electrode 6022 of subpixel in the second color cannot overlap the second electrode of the seventh transistor T7 of the subpixel drive circuit of subpixel in the second color, but the second electrode of the seventh transistor T7 of subpixel in the second color can overlap the third body electrode 6031 of subpixel in the third color. The third connecting electrode 6032 of subpixel in the third color can overlap the second electrode of the seventh transistor T7 of the subpixel drive circuit of subpixel in the third color.

[0268] The present description also provides in some embodiments a display device that includes the display substrate mentioned above.

[0269] According to the aforementioned display substrate, through the first shielding member 404, it is possible to reduce the influence caused by the change in the signal transmitted through the target data line pattern on the performance of the first transistor T1, thereby reducing the influence of the coupling between a gate electrode (i.e., 203g) of the drive transistor and the target data line pattern and reducing the vertical crossover, and improving the display effect of the display substrate during display. Furthermore, in the display panel according to the embodiments of the present description, when the first shielding member 404 is coupled to the initial signal line pattern, it is able to, in addition to providing the first shielding member 404 with a fixed potential, increase a voltage across the initial signal line pattern and provide a higher voltage. Petition 870260037267, dated 04 / 22 / 2026, page 86 / 259 82 / 112 stable for the initialization signal transmitted in the initialization signal line standard, in order to thereby improve the operating performance of the subpixel drive circuit.

[0270] Thus, when the display device includes the aforementioned display substrate, it can have the same beneficial effect, which will not be repeatedly described here.

[0271] It should be noted that the display device can be any product or component that has a display function, for example, television, display, digital photo frame, mobile phone or tablet computer.

[0272] The present description further provides in some embodiments a method for manufacturing the aforementioned display substrate, which includes forming a plurality of subpixels on the base 50 in a matrix form. The subpixel includes: a data line pattern (for example, DATA1 in Figure 3) that extends in a first direction; A startup signal line pattern (e.g., VINT1 in Figure 3) that includes a portion extending in a second direction that intersects the first direction, and configured to transmit a startup signal at a fixed potential; and a subpixel drive circuit. The subpixel drive circuit includes a drive transistor (e.g., T3 in Figure 3), a first transistor T1 coupled to a gate electrode of the drive transistor, and a first shield member 404 coupled to the startup signal line pattern. An orthogonal projection of the first shield member 404 onto base 50 may be located between an orthogonal projection of the first transistor T1 onto base 50 and an orthogonal projection of a target data line pattern (e.g., DATA2 in Figure 3) onto base 50. A next subpixel adjacent to the subpixel in the second direction. Petition 870260037267, dated 04 / 22 / 2026, page 87 / 259 83 / 112 includes the target data line pattern.

[0273] When the display substrate is manufactured using the method mentioned above in accordance with the embodiments of the present description, the subpixel drive circuit is provided with the first shield member 404 coupled in the initialization signal line pattern (e.g., VINT1 in Figure 3), so as to provide the first shield member 404 with the same fixed potential as the initialization signal.Furthermore, the orthogonal projection of the first shielding member 404 onto the base 50 can be located between the orthogonal projection of the first transistor T1 onto the base 50 and the orthogonal projection of the target data line pattern (e.g., DATA2 in Figure 3) onto the base 50, so that this is able to reduce, through the first shielding member 404, the influence caused by the change in the signal transmitted through the target data line pattern on the performance of the first transistor T1, thereby reducing the coupling effect between a gate electrode (i.e., 203g) of the drive transistor and the target data line pattern and reducing the vertical crosshair, and improving the display effect of the display substrate during display.

[0274] Furthermore, during the fabrication of the display substrate using the above-mentioned method according to the embodiments of the present description, when the first shield member 404 is coupled in the initialization signal line pattern, this is able to, in addition to providing the first shield member 404 with the fixed potential, increase a voltage across the initialization signal line pattern and provide a more stable voltage for the initialization signal transmitted in the initialization signal line pattern, thereby improving the operating performance of the subpixel drive circuit.

[0275] As shown in Figure 16, the present description still Petition 870260037267, dated 04 / 22 / 2026, page 88 / 259 84 / 112 provides in some embodiments a display substrate, which includes a base 50 and a plurality of subpixels arranged on the base in a matrix form. The subpixel includes: a data line pattern (e.g., DATA1) that extends in a first direction; A VDD power line pattern that includes a portion extending in the first direction; and a subpixel drive circuit. The subpixel drive circuit includes two switching transistors (e.g., a fourth transistor T4 and a fifth transistor T5), a drive transistor (e.g., a third transistor T3), and a storage capacitor Cst. A first electrode Cst1 of the storage capacitor Cst is coupled to a gate electrode of the drive transistor (e.g., a gate electrode 203g of the third transistor T3), and a second electrode plate Cst2 of the storage capacitor Cst is coupled to the VDD power line pattern.The second electrodes of the two switching transistors (e.g., a drain electrode D4 of the fourth transistor T4 and a drain electrode D5 of the fifth transistor T5) are coupled and a first electrode of the drive transistor (e.g., a source electrode S3 of the third transistor T3). An orthogonal projection of the second electrode of at least one of the two switching transistors onto base 50 at least partially overlaps an orthogonal projection of the power line pattern VDD onto base 50 and at least partially overlaps an orthogonal projection of the second electrode plate Cst2 of the storage capacitor Cst onto base 50.

[0276] To be specific, usually the display substrate may include the plurality of subpixels arranged in a matrix form, and each subpixel may include the data line pattern (e.g., DATA1) extending in the first direction, and the line pattern of. Petition 870260037267, dated 04 / 22 / 2026, page 89 / 259 85 / 112 VDD power supply, at least a portion of which extends in the first direction. For example, the first direction may include a Y direction, and a second direction may include an X direction.

[0277] It should be appreciated that the power line standard VDD can have various structures. For example, the VDD feedline pattern can be of a grid-like structure, and the VDD grid-like feedline pattern can include the portion that extends in the first direction.

[0278] Each subpixel may further include subpixel drive circuits, and light-emitting elements that correspond to the subpixel drive circuits respectively. The light-emitting element may include an anode, a layer of organic light-emitting material, and a cathode laminated one upon the other. The anode of the light-emitting element may be coupled to the corresponding subpixel drive circuit, and the light-emitting element may emit light under the control of a drive signal from the subpixel drive circuit.

[0279] More specifically, as shown in Figure 16, when the subpixel drive circuit includes the aforementioned 7T1C-based subpixel drive circuit, the gate electrode 203g of the third transistor T3 (i.e., the drive transistor) can be reused as the first electrode plate Cst1 of the storage capacitor Cst, and the second electrode plate Cst2 of the storage capacitor Cst can be arranged on one side of the first electrode plate Cst1 furthest from the base. An orthogonal projection of the first electrode plate Cst1 onto the base can at least partially overlap the orthogonal projection of the second electrode plate Cst2 onto the base, and the orthogonal projection of the second electrode plate Cst2 onto the base can at least partially overlap the orthogonal projection of the second electrode of Petition 870260037267, dated 04 / 22 / 2026, page 90 / 259 86 / 112 at least one of the fourth transistor T4 and the fifth transistor T5 on base 50 and the orthogonal projection of the VDD power line pattern on base 50.

[0280] Based on the specific structure above of the display substrate, in the display substrate according to embodiments of the present description, when the second electrode plate Cst2 of the storage capacitor Cst is coupled to the VDD power line pattern, the second electrode plate Cst2 of the storage capacitor Cst can have the same fixed potential as the power transmitted in the VDD power line pattern. Furthermore, when the second electrodes of the two switching transistors are coupled to the first electrode of the drive transistor, and the orthogonal projection of the second electrode of at least one of the two switching transistors onto the base 50 at least partially overlaps the orthogonal projection of the VDD power line pattern onto the base 50, and at least partially overlaps the orthogonal projection of the second electrode plate Cst2 of the storage capacitor Cst onto the base 50,The second electrode plate Cst2 of the storage capacitor Cst and the power line pattern VDD can shield the second electrode of at least one of the two switching transistors, so as to reduce the crossover to the second electrode of at least one of the two switching transistors due to a signal on the other conductive pattern (e.g., a signal line pattern) surrounding at least one of the two switching transistors, thereby reducing the crossover to the first electrode of the driving transistor.

[0281] As shown in Figure 16, in some embodiments of the present description, the second electrodes of the two switching transistors (for example, the fourth transistor T4 and the fifth transistor T5) Petition 870260037267, dated 04 / 22 / 2026, page 91 / 259 87 / 112 can be integrally formed with the first electrode of the drive transistor (e.g., the third transistor T3). A resulting integral structure may include a first conductive member 108 extending in the first direction, and an orthogonal projection of the first conductive member 108 onto the base may overlap the orthogonal projection of the power line pattern VDD onto the base and the orthogonal projection of the second electrode plate Cst2 of the storage capacitor Cst onto the base 50 in a first overlap region, which does not overlap the orthogonal projection of the data line pattern (e.g., DATA1) onto the base 50.

[0282] To be specific, when the second electrodes of the two switching transistors are formed integrally with the first electrode of the driving transistor, this is capable of forming the second electrodes of the two switching transistors and the first electrode of the driving transistor through a single patterning process.

[0283] In the aforementioned display substrate according to the embodiments of the present description, the integral structure may include a first conductive member 108 extending in the first direction, the orthogonal projection of the data line pattern onto the base may be located on one side of the orthogonal projection of the first conductive member 108 onto the base furthest from the orthogonal projection of the drive transistor onto the base, and the orthogonal projection of the first conductive member 108 onto the base may overlap the orthogonal projection of the VDD power line pattern onto the base and the orthogonal projection of the second electrode plate Cst2 of the storage capacitor Cst onto the base 50 in the first overlap region. In this mode, the second electrode plate Cst2 of the storage capacitor Cst and the VDD power line pattern may shield the first conductive member 108, so as to reduce Petition 870260037267, dated 04 / 22 / 2026, page 92 / 259 88 / 112 the crossover line to the first conducting member 108 due to a signal transmitted in the data line pattern, in order to thereby reduce the crossover line to the first electrode of the drive transistor.

[0284] As shown in Figure 16, in some embodiments of the present description, the orthogonal projection of the first electrode of the drive transistor onto the base 50 may be located within the orthogonal projection of the second electrode plate Cst2 of the storage capacitor Cst onto the base.

[0285] In this arrangement mode, the second electrode plate Cst2 of the storage capacitor Cst can completely cover the first electrode of the drive transistor, so as to reduce the crossover line to the first electrode of the drive transistor due to the signal transmitted in the data line pattern in a more effective way.

[0286] As shown in Figures 16 and 17, in some embodiments of the present description, the subpixel may further include a GATE gate line pattern and an EM light emission control signal line pattern, each extending in a second direction that intersects the first direction. The subpixel drive circuit may further include a first transistor T1 and a sixth transistor T6, and the two switching transistors may include a fourth transistor T4 and a fifth transistor T5.

[0287] A 204g gate electrode of the fourth transistor T4 can be coupled in the GATE gate line pattern, a first electrode of the fourth transistor T4 can be coupled in the data line pattern (e.g., DATA1), and a second electrode of the fourth transistor T4 can be coupled to a second electrode of the fifth transistor T5. A 205g gate electrode of the fifth transistor T5 can be coupled in the EM light emission control signal line pattern, and a first electrode of the fifth transistor T5 can be coupled in the pattern Petition 870260037267, dated 04 / 22 / 2026, page 93 / 259 89 / 112 VDD power supply line.

[0288] A gate electrode 201g of the first transistor T1 can be coupled in the gate line pattern, and a second electrode of the first transistor T1 can be coupled to the gate electrode of the drive transistor. A first electrode of the first transistor T1, a first electrode of the sixth transistor T6, and the second electrode of the drive transistor can be integrally formed, and a resulting integral structure can include a second conductive member 109 extending in the first direction. A gate electrode 206g of the sixth transistor T6 can be coupled in the EM light-emitting control signal line pattern, and a second electrode of the sixth transistor T6 can be coupled to the subpixel light-emitting element.

[0289] An orthogonal projection of a channel region (e.g., 103pg in Figure 18) of the drive transistor onto the base can be arranged between the orthogonal projection of the first conducting member 108 onto the base 50 and an orthogonal projection of the second conducting member 109 onto the base 50. Furthermore, in the second direction, a minimum distance between the orthogonal projection of the channel region of the drive transistor onto the base and the orthogonal projection of the first conducting member 108 onto the base can be smaller than a minimum distance between the orthogonal projection of the channel region onto the base 50 and the orthogonal projection of the second conducting member 109 onto the base.

[0290] To be specific, on the display substrate, the plurality of subpixels can be arranged in a matrix form, that is, in rows and columns. Each row of subpixels can include a plurality of subpixels arranged in the second direction, and each column of subpixels can include a plurality of subpixels arranged in the first direction that intersects the second direction. Subpixel drive circuits Petition 870260037267, dated 04 / 22 / 2026, p. 94 / 259 90 / 112 of the subpixels in each column can be arranged between the data row patterns of the subpixels in the column and the data row patterns of the subpixels in a next column adjacent to the column.

[0291] It should be appreciated that, in the second direction, the minimum distance between the orthogonal projection of the channel region of the drive transistor onto the base and the orthogonal projection of the first conducting member 108 onto the base may refer to a distance in the second direction between an edge of the orthogonal projection of the channel region of the drive transistor onto the base closest to the orthogonal projection of the first conducting member 108 onto the base and the orthogonal projection of the first conducting member 108 onto the base. In the second direction, the minimum distance between the orthogonal projection of the channel region onto the base 50 and the orthogonal projection of the second conducting member 109 onto the base may refer to a distance in the second direction between an edge of the orthogonal projection of the channel region of the drive transistor onto the base closest to the orthogonal projection of the second conducting member 109 onto the base and the orthogonal projection of the second conducting member 109 onto the base.

[0292] More specifically, the subpixel drive circuit of each subpixel can be arranged between two adjacent data line patterns (e.g., DATA1 and DATA2). The data transmitted in the two data line patterns can change, and when the data changes, a crossover can easily occur to the gate electrode of the drive transistor of the subpixel drive circuit, as shown in Figure 25, and thereby the operational stability of the drive transmission can be adversely affected.

[0293] In the embodiments of the present description, the fourth transistor T4, the fifth transistor T5, the first transistor T1, and the sixth transistor T6 can be arranged in a region surrounding the transistor of Petition 870260037267, dated 04 / 22 / 2026, page 95 / 259 91 / 112 drive, one of the two data line patterns (e.g., DATA1) can be arranged on one side of each of the fourth transistor T4 and the fifth transistor T5 furthest from the drive transistor, and the other of the two data line patterns (e.g., DATA2) can be arranged on one side of each of the first transistor T1 and the sixth transistor T6 furthest from the drive transistor.Furthermore, the orthogonal projection of the channel region (e.g., 103pg in Figure 18) of the drive transistor onto the base can be arranged between the orthogonal projection of the first conducting member 108 onto the base 50 and the orthogonal projection of the second conducting member 109 onto the base 50, and the minimum distance between the orthogonal projection of the channel region of the drive transistor onto the base and the orthogonal projection of the first conducting member 108 onto the base can be smaller than the minimum distance between the orthogonal projection of the channel region onto the base and the orthogonal projection of the second conducting member 109 onto the base. In this way, if there is an appropriate distance between the channel region of the drive transistor and DATA1, it is possible to increase the distance between the channel region of the drive transistor and DATA2 to the greatest extent, thereby reducing the crossover to the drive transistor caused by DATA2 to a better degree.

[0294] Furthermore, since a portion of the drive transistor channel region near DATA1 is covered by the VDD power line pattern, this is able to effectively reduce the crossover to the drive transistor channel region caused by DATA1. Thus, in the embodiments of the present description, the crossover can be relatively small, even when the distance between the drive transistor channel region and DATA is relatively small.

[0295] In addition, when the second electrode plate Cst2 of Petition 870260037267, dated 04 / 22 / 2026, page 96 / 259 The 92 / 112 storage capacitor Cst has the same fixed potential as the power supply transmitted in the VDD power line pattern, and the orthogonal projection of the first conductive member 108 onto the base overlaps the orthogonal projection of the VDD power line pattern onto the base and the orthogonal projection of the second electrode plate Cst2 of the storage capacitor Cst onto the base 50 in the first overlap region. The second electrode plate Cst2 of the storage capacitor Cst and the VDD power line pattern can shield the first conductive member 108, so as to reduce the crosshair to the first conductive member 108 caused by the signal transmitted in DATA1, thereby reducing the crosshair to the first electrode and the channel region of the drive transistor.

[0296] As shown in Figure 16, in some embodiments of the present description, the subpixel may further include a GATE gate line pattern and an EM light emission control signal line pattern extending in a second direction that intersects the first direction. The subpixel drive circuit may also include a first transistor T1 and a sixth transistor T6, and the two switching transistors may include a fourth transistor T4 and a fifth transistor T5.

[0297] A gate electrode 204g of the fourth transistor T4 can be coupled in the GATE gate line pattern, a first electrode of the fourth transistor T4 can be coupled in the data line pattern (e.g., DATA1), and a second electrode of the fourth transistor T4 can be coupled to a second electrode of the fifth transistor T5. A gate electrode 205g of the fifth transistor T5 can be coupled in the EM light emission control signal line pattern, and a first electrode of the fifth transistor T5 can be coupled in the VDD power line pattern.

[0298] A gate electrode 201g of the first transistor T1 can be Petition 870260037267, dated 04 / 22 / 2026, page 97 / 259 93 / 112 coupled in the gate line pattern, and a second electrode of the first transistor T1 can be coupled to the gate electrode of the drive transistor. A first electrode of the first transistor T1, a first electrode of the sixth transistor T6, and the second electrode of the drive transistor can be integrally formed, and a resulting integral structure can include a second conductive member 109 extending in the first direction. A gate electrode 206g of the sixth transistor T6 can be coupled in the EM light emission control signal line pattern, and a second electrode of the sixth transistor T6 can be coupled to the subpixel light emitting element.

[0299] An orthogonal projection of a channel region (e.g., 103pg in Figure 18) of the drive transistor onto the base may be disposed between the orthogonal projection of the first conducting member 108 onto the base and an orthogonal projection of the second conducting member 109 onto the base. The first electrode and the second electrode of the drive transistor may each include a first portion extending in the second direction, and the length of the first portion of the first electrode in the second direction may be different from the length of the first portion of the second electrode in the second direction.

[0300] To be specific, when the first electrode and the second electrode of the drive transistor each include the first portion extending in the second direction, and the length of the first portion of the first electrode in the second direction is different from the length of the first portion of the second electrode in the second direction, the following two circumstances may exist.

[0301] In a first circumstance, the length H1 of the first portion of the first electrode in the second direction may be smaller than the length H2 of the first portion of the second Petition 870260037267, dated 04 / 22 / 2026, page 98 / 259 94 / 112 electrode in the second direction. In this respect, the channel region (e.g., 103pg in Figure 18) of the drive transistor can be arranged close to the data line pattern (e.g., DATA1) of the subpixel to which the drive transistor belongs and further away from the data line pattern (e.g., DATA2) of a next subpixel adjacent to the subpixel to which the drive transistor belongs in the second direction, so as to increase the distance between the channel region of the drive transistor and DATA2 to the greatest degree in the case of ensuring an appropriate distance between the channel region of the drive transistor and DATA1, thereby reducing the crosshair to the drive transistor caused by DATA2 in a better way.Furthermore, since the first conductive member 108 is shielded by the second electrode plate Cst2 of the storage capacitor Cst and the power line pattern VDD, this is able to reduce the crossover to the first conductive member 108 due to the signal transmitted in DATA1, thereby reducing the crossover to the first electrode and the channel region of the drive transistor.

[0302] In a second circumstance, the length of the first portion of the first electrode in the second direction may be greater than the length of the first portion of the second electrode in the second direction. In this respect, the channel region (e.g., 103pg in Figure 18) of the drive transistor may be disposed further from the data line pattern (e.g., DATA1) of the subpixel to which the drive transistor belongs and disposed closer to the data line pattern (e.g., DATA2) of a next subpixel adjacent to the subpixel to which the drive transistor belongs in the second direction, so as to increase the distance between the channel region of the drive transistor and DATA1 to the greatest degree in the case of ensuring an appropriate distance between the channel region of the driver transistor and Petition 870260037267, dated 04 / 22 / 2026, page 99 / 259 95 / 112 drive and DATA2, thereby reducing the crosshair to the drive transistor caused by DATA1 to a better degree. Furthermore, when the display substrate includes a first shielding member to completely shield DATA2 from the second conductive member 109, this is able to reduce the crosshair to the second conductive member 109 due to the signal transmitted in DATA2, thereby reducing the crosshair to the second electrode and the channel region of the drive transistor.

[0303] As shown in Figure 16, in some embodiments of the present description, the subpixel may further include a startup signal line pattern (e.g., VINT1) that includes a portion extending in a second direction that intersects the first direction, wherein the startup signal line pattern is configured to transmit a startup signal at a fixed potential.

[0304] The subpixel drive circuit may further include a second transistor T2 coupled to the gate electrode of the drive transistor. The second transistor T2 may include: a first semiconductor pattern, a second semiconductor pattern, and a third conductor pattern coupled to the first semiconductor pattern and the second semiconductor pattern, the electrical conductivity of the third conductor pattern being greater than the electrical conductivity of the first semiconductor pattern and the second semiconductor pattern; and a first gate electrode pattern and a second gate electrode pattern coupled to each other.An orthogonal projection of the first gate electrode pattern onto the base can at least partially overlap an orthogonal projection of the first semiconductor pattern onto the base, and an orthogonal projection of the second gate electrode pattern onto the base can at least partially overlap an orthogonal projection of the second semiconductor pattern onto the base. An orthogonal projection of the third conductor pattern onto the base. Petition 870260037267, dated 04 / 22 / 2026, page 100 / 259 96 / 112 may not overlap the orthogonal projection of the first gate electrode pattern onto the base and the orthogonal projection of the second gate electrode pattern onto the base. The orthogonal projection of the third conductor pattern onto the base may at least partially overlap the orthogonal projection of the initial signal line pattern onto the base.

[0305] To be specific, as shown in Figure 16, the second transistor T2 may be of a dual-gate structure. The first semiconductor pattern and the second semiconductor pattern of the second transistor may form a channel region (corresponding to a signal location 102pg in Figure 18) of the second transistor T2, and the third conductor pattern 102px of the second transistor may have higher electrical conductivity than the first semiconductor pattern and the second semiconductor pattern due to doping of the third conductor pattern 102px. The first gate electrode pattern and the second gate electrode pattern of the second transistor T2 may cover the first semiconductor pattern and the second semiconductor pattern respectively, and together serve as the gate electrode 202g of the second transistor T2.

[0306] In the second transistor T2 with the above structure, since the third conductor pattern 102px has excellent electrical conductivity and is not covered by the gate electrode pattern, it can be easily coupled to the other neighboring conductor patterns, and through this, a crossover line can occur. According to the embodiments of the present description, when the orthogonal projection of the third conductor pattern onto the base 50 at least partially overlaps the orthogonal projection of the startup signal line pattern onto the base 50, it is able for the startup signal line pattern to shield the third conductor pattern 102px. Since the startup signal at a fixed potential is transmitted in the startup signal line pattern, Petition 870260037267, dated 04 / 22 / 2026, page 101 / 259 97 / 112 is capable of reducing the coupling effect between the third 102px driver pattern and the other neighboring driver patterns in a better way, thereby providing the display substrate with more stable operating performance.

[0307] As shown in Figures 16 and 18, in some embodiments of the present description, the subpixel drive circuit may further include a first extension member that extends from the first semiconductor pattern and has an electrical conductivity higher than the first semiconductor pattern. The first extension member may include a first portion 61, a second portion 62, and a third portion 63. The first portion 61 and the third portion 63 may each extend in the first direction, and the second portion 62 may extend in the second direction. One end of the second portion 62 may be coupled to the first portion 61, the other end of the second portion 62 may be coupled to the third portion 63, and one end of the third portion 63 furthest from the second portion 62 may be coupled to the first transistor T1.

[0308] To be specific, the first extension member and the first semiconductor pattern can be formed through a single patterning process, and after the formation of the first semiconductor pattern, the first extension member can be doped so that the electrical conductivity of the first extension member is higher than that of the first semiconductor pattern.

[0309] After adding the first shielding member 404, via the first extension member with the aforementioned structure, it is able to reduce the influence on the performance of the first transistor T1 and the second transistor T2 caused by the change in the signal transmitted through the target data line pattern when the second transistor T2 is coupled to the first transistor T1. Petition 870260037267, dated 04 / 22 / 2026, page 102 / 259 98 / 112 and the gate electrode of the drive transistor through the first extension member, thereby relieving the coupling effect between a gate electrode (i.e., 203g) of the drive transistor and the target data line pattern and reducing vertical crosstalk, and improving the display effect of the display substrate during display.

[0310] In some embodiments of the present description, the first transistor may include: a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern coupled to the fourth semiconductor pattern and the fifth semiconductor pattern, the electrical conductivity of the sixth conductor pattern being greater than the electrical conductivity of the fourth semiconductor pattern and the fifth semiconductor pattern; and a third gate electrode pattern and a fourth gate electrode pattern coupled to each other.An orthogonal projection of the third gate electrode pattern onto the base may partially overlap an orthogonal projection of the fourth semiconductor pattern onto the base, an orthogonal projection of the fourth gate electrode pattern onto the base may partially overlap an orthogonal projection of the fifth semiconductor pattern onto the base, and an orthogonal projection of the sixth conductor pattern onto the base may not overlap the orthogonal projection of the third gate electrode pattern onto the base and the orthogonal projection of the fourth gate electrode pattern onto the base.

[0311] To be specific, as shown in Figure 16, the first transistor may be of a double-gate structure. The fourth semiconductor pattern and the fifth semiconductor pattern of the first transistor may form a channel region (corresponding to signal 101pg in Figure 18) of the first transistor T1, and the sixth conductor pattern. Petition 870260037267, dated 04 / 22 / 2026, page 103 / 259 99 / 112 The 101px electrode of the first transistor may have higher electrical conductivity than the fourth and fifth semiconductor electrodes due to doping of the sixth electrode (101px). The third electrode and fourth gate electrode patterns of the first transistor may cover the fourth and fifth semiconductor patterns respectively, and together form the 201g gate electrode of the first transistor T1.

[0312] As shown in Figure 19, in some embodiments of the present description, the subpixel may further include a startup signal line pattern (e.g., VINT1). The startup signal line may include a portion extending in a second direction that intersects the first direction, and is configured to transmit a startup signal at a fixed potential. The subpixel drive circuit may further include a first shield member 404 coupled to the startup signal line pattern, and an orthogonal projection of the first shield member 404 onto the base 50 may at least partially overlap the orthogonal projection of the sixth conductor pattern 101px onto the base 50.

[0313] In the embodiments of the present description, when the orthogonal projection of the first shielding member 404 onto the base 50 at least partially overlaps the orthogonal projection of the sixth conductor pattern 101px onto the base 50, the sixth conductor pattern 101px can be shielded by the first shielding member 404. Furthermore, since the first shielding member 404 has a fixed potential, this is able to reduce the coupling effect between the sixth conductor pattern 101px and the other conductor patterns adjacent to the sixth conductor pattern 101px in a better way, thereby providing the display substrate with more stable operating performance.

[0314] As shown in Figure 20, in some forms of Petition 870260037267, dated 04 / 22 / 2026, page 104 / 259 100 / 112 present description, the subpixel may also include a startup signal line pattern (e.g., VINT1). The startup signal line pattern may include a portion that extends in a second direction that intersects the first direction, and the startup signal line pattern is configured to transmit a startup signal at a fixed potential.

[0315] The subpixel drive circuit may further include a first 404 shielding member coupled to the initial signal line pattern, and a second 301 shielding member coupled to the first 404 shielding member. An orthogonal projection of the second 301 shielding member onto the base may at least partially overlap the orthogonal projection of the sixth conductor pattern onto the base.

[0316] To be specific, when the orthogonal projection of the second shielding member 301 onto the base 50 at least partially overlaps the orthogonal projection of the sixth conductor pattern 101px onto the base 50, the sixth conductor pattern 101px can be shielded by the second shielding member 301. Furthermore, since the second shielding member 301 is coupled to the first shielding member 404, the second shielding member 301 can have a fixed potential, so that this is able to reduce the coupling effect between the sixth conductor pattern 101px and the other conductor patterns adjacent to the sixth conductor pattern 101px in a better way, thereby providing the display substrate with stable operating performance.

[0317] Thus, in the display substrate according to the embodiments of the present description, as the first shielding member 404 and the second shielding member 301 have a fixed potential, so as to be able to prevent or reduce a parasitic capacitance generated between the first transistor T1 and the standard Petition 870260037267, dated 04 / 22 / 2026, p. 105 / 259 101 / 112 of the target data line (e.g., DATA2) in a better way, in order to thereby prevent or reduce vertical crosstalk.

[0318] As shown in Figures 21 and 22, in some embodiments of the present description, the plurality of subpixels can be arranged in a plurality of lines, and each line of subpixels can include a plurality of subpixels arranged in the second direction. The initialization signal line patterns of the subpixels in the same line can be sequentially coupled to each other to form an initialization signal line that corresponds to the subpixels in the line. The first 404 shielding member can extend in the first direction, and can be coupled to two initialization signal lines adjacent to the first 404 shielding member.

[0319] In some embodiments of the present description, a shape of the power line pattern can be adjusted according to practical need. For example, in the second direction, a width of a portion of the power line pattern near the channel region of the drive transistor can be smaller than a width of a portion of the power line pattern further from the channel region of the drive transistor, so as to reduce the influence of the power line pattern on the gate electrode of the drive transistor at a position in close proximity to the channel region of the drive transistor.

[0320] In some embodiments of the present description, as shown in Figure 23, the display substrate may be provided with a 408 offset pattern coupled in parallel to the power line pattern, so as to improve the transmission performance of the power line pattern. It should be appreciated that the 408 offset pattern may be arranged in the same layer, and made of the same material, as the third conductive connecting member, so as to form the 408 offset pattern and Petition 870260037267, dated 04 / 22 / 2026, page 106 / 259 102 / 112 the third connecting conductor member through a single standardization process.

[0321] In some embodiments of the present description, in a subpixel, the orthogonal projection of the VDD feed line pattern onto the base may completely cover the orthogonal projection of the first conductive member 108 onto the base.

[0322] In some embodiments of the present description, in a subpixel, the orthogonal projection of the VDD power line pattern onto the base may cover the orthogonal projections of the first semiconductor pattern, the second semiconductor pattern, and the third conductor pattern of the second transistor T2 onto the base, and cover at least part of the orthogonal projection of the first electrode of the second transistor T2 onto the base, and cover at least part of the orthogonal projection of the second electrode of the second transistor T2 onto the base.

[0323] In some embodiments of the present description, the first 404 shielding member may be an extension structure that extends from the initial signal line pattern.

[0324] To be specific, when the first shielding member 404 is the extension structure extending from the initial signal line pattern, it is possible to form the first shielding member 404 and the initial signal line pattern through a single patterning process, thereby simplifying the manufacturing process of the display substrate in a better way.

[0325] As shown in Figure 20, in some embodiments of the present description, the first shielding member 404 and the initial signal line pattern can be arranged in different layers. The orthogonal projection of the first shielding member 404 onto the base 50 can overlap the orthogonal projection of the initial signal line pattern onto the base 50 in a first overlapping region, the first shielding member is coupled to Petition 870260037267, dated 04 / 22 / 2026, page 107 / 259 103 / 112 standard initial signal line through a first track hole arranged in the first overlap region.

[0326] The second shielding member 301 and the first shielding member 404 can be arranged in different layers. The orthogonal projection of the second shielding member 301 onto the base 50 can overlap the orthogonal projection of the first shielding member 404 onto the base 50 in a second overlapping region, the second shielding member 301 is coupled to the first shielding member 404 through a second wayhole arranged in the second overlapping region.

[0327] To be specific, the first shielding member 404 and the initial signal line pattern can be arranged in the same layer or in different layers. When the first shielding member 404 is arranged in a different layer from the initial signal line pattern, the orthogonal projection of the first shielding member 404 onto the base 50 can overlap the orthogonal projection of the initial signal line pattern onto the base 50 in the first overlap region. In this mode, the first shielding member 404 can be coupled to the initial signal line through the first via hole in the first overlap region. Similarly, the second shielding member 301 and the first shielding member 404 can be arranged in the same layer or in different layers.When the second shielding member 301 is arranged in a different layer from the first shielding member 404, the orthogonal projection of the second shielding member 301 onto the base 50 can overlap the orthogonal projection of the first shielding member 404 onto the base 50 in the second overlap region. In this mode, the second shielding member 301 can be coupled to the first shielding member 404 through the second wayhole in the second region. Petition 870260037267, dated 04 / 22 / 2026, page 108 / 259 104 / 112 overlap.

[0328] In some embodiments of the present description, the first shielding member 404 may be made of the same material as the data line pattern.

[0329] In some embodiments of the present description, the display substrate may include a first interlayer insulation layer, and the first 404 shielding member and data line pattern may be arranged on a surface of the first interlayer insulation layer furthest from the base.

[0330] To be specific, when the first 404 shielding member is arranged as mentioned above, it is able to simultaneously form the first 404 shielding member and the data line pattern on the surface of the first interlayer insulation layer furthest from the base through a single patterning process, and omit an additional patterning process to form the first 404 shielding member, thereby simplifying the display substrate manufacturing process in a better way and reducing the manufacturing cost.

[0331] In some embodiments of the present description, the second shielding member 301 may be made of the same material as the initial signal line pattern.

[0332] In some embodiments of the present description, the display substrate may further include a second interlayer insulation layer, and the second shielding member 301 and the initial signal line pattern may be arranged on a surface of the second interlayer insulation layer further from the base.

[0333] To be specific, when the second shielding member 301 and the initial signal line pattern (e.g., VINT1 in Figure 3) are made of the same material and arranged on the surface of the second interlayer insulation layer Petition 870260037267, dated 04 / 22 / 2026, page 109 / 259 105 / 112 further from the base, this is capable of simultaneously forming the second shielding member 301 and the initial signal line pattern through a single patterning process, and omitting an additional patterning process to form the second shielding member 301, thereby simplifying the display substrate manufacturing process in a better way and reducing the manufacturing cost.

[0334] In some embodiments of the present description, the first electrode plate Cst1 of the storage capacitor Cst can be reused as the gate electrode of the drive transistor, the second electrode plate Cst2 of the storage capacitor Cst can be made of the same material as the second shielding member 301, and the second electrode plate Cst2 of the storage capacitor Cst can be arranged on the surface of the second interlayer insulation layer furthest from the base 50.

[0335] To be specific, the storage capacitor Cst of the subpixel drive circuit can include the first electrode plate Cst1 and the second electrode plate Cst2 arranged opposite each other. The first electrode plate Cst1 can be coupled to the gate electrode of the drive transistor, and the second electrode plate Cst2 can be coupled to the VDD power line pattern. During the arrangement of the storage capacitor Cst, the first electrode plate Cst1 can be directly reused as the gate electrode of the drive transistor. In this way, it is possible not only to ensure that the storage capacitor Cst is coupled to the gate electrode of the drive transistor, but also to reduce the space occupied by the subpixel drive circuit, thereby improving the resolution of the display substrate.Furthermore, when the second electrode plate Cst2 of the storage capacitor Cst is placed on the surface of... Petition 870260037267, dated 04 / 22 / 2026, page 110 / 259 106 / 112 second interlayer insulation furthest from the base, the second electrode plate Cst2 of the Cst storage capacitor can be formed simultaneously through a single patterning with the second shielding member 301 and the initial signal line pattern, so that this is able to simplify the manufacturing process of the display substrate in a better way, and reduce the manufacturing cost.

[0336] In some embodiments of the present description, the subpixel may further include a reset signal line pattern (e.g., RST1) extending in a second direction that intersects the first direction. The subpixel drive circuit may further include: a first conductor connecting member 405, an orthogonal projection of which onto base 50 at least partially overlaps the orthogonal projection of the sixth conductor pattern 101px onto base 50; and a second transistor T2, a first electrode (e.g., a source electrode S2) which is coupled to the initialization signal line pattern (e.g., VINT1) via the first conductor connecting member 405, a second electrode (e.g., a drain electrode D2) which is coupled to the gate electrode of the drive transistor, and a gate electrode 202g which is coupled to the reset signal line pattern (e.g., RST1).

[0337] To be specific, the first conductive connecting member 405 can be made of a metallic material, and can be formed through a single patterning process with the data line pattern.

[0338] When the orthogonal projection of the first 405 conductor connecting member onto the base 50 at least partially overlaps the orthogonal projection of the sixth 101px conductor pattern onto the base 50, so that the sixth 101px conductor pattern can be shielded by the first 405 conductor connecting member. Furthermore, as the first 405 conductor connecting member is coupled Petition 870260037267, dated 04 / 22 / 2026, page 111 / 259 107 / 112 in the initialization signal line pattern, so that the first conductor connection member 405 can have a fixed potential, so as to reduce a coupling effect between the sixth conductor pattern 101px and the other conductor patterns adjacent to the sixth conductor pattern 101px in a better way, to thereby provide the display substrate with more stable operating performance.

[0339] As shown in Figure 16, in some embodiments of the present description, the subpixel may further include a GATE gate line pattern, an EM light emission control signal line pattern, a reset signal line pattern (e.g., RST1) and an initialization signal line pattern (e.g., VINT1). The GATE gate line pattern, the EM light emission control signal line pattern, the reset signal line pattern and the initialization signal line pattern may extend in the second direction intersecting the first direction.The two switching transistors may include a fourth transistor T4 and a fifth transistor T5.

[0340] The subpixel drive circuit may also include a first transistor T1, a second transistor T2, a sixth transistor T6, and a seventh transistor T7. A gate electrode of the drive transistor (e.g., a gate electrode 203g of the third transistor T3) may be coupled to a second electrode of the first transistor T1, a first electrode of the drive transistor may be coupled to a second electrode of the fifth transistor T5, and a second electrode of the drive transistor may be coupled to a first electrode of the first transistor T1. A gate electrode 201g of the first transistor T1 may be coupled in the GATE gate line pattern. A gate electrode 202g of the second transistor T2 may be coupled in the reset signal line pattern, a first electrode of the second transistor T2 may be coupled in the initialization signal line pattern, and a second electrode of the second transistor T2 may be Petition 870260037267, dated 04 / 22 / 2026, p. 112 / 259 108 / 112 coupled to the gate electrode of the drive transistor. A gate electrode 204g of the fourth transistor T4 can be coupled to the GATE gate line pattern, a first electrode of the fourth transistor T4 can be coupled to the data line pattern (e.g., DATA1 in the figure), and a second electrode of the fourth transistor T4 can be coupled to the first electrode of the drive transistor. A gate electrode 205g of the fifth transistor T5 can be coupled to the EM light emission control signal line pattern, and a first electrode of the fifth transistor T5 can be coupled to the VDD power supply line pattern. A gate electrode 206g of the sixth transistor T6 can be coupled to the EM light emission control signal line pattern, a first electrode of the sixth transistor T6 can be coupled to the second electrode of the drive transistor, and a second electrode of the sixth transistor T6 can be coupled to the subpixel light emission element.A 207g gate electrode of the seventh transistor T7 can be coupled to the reset signal line pattern (e.g., RST2) of a next adjacent subpixel in the first direction, a first electrode of the seventh transistor T7 can be coupled to the initialization signal line pattern (e.g., VINT2) of the next adjacent subpixel, and a second electrode of the seventh transistor T7 can be coupled to the light-emitting element of the subpixel.

[0341] To be specific, on the display substrate, the plurality of subpixels can be arranged in a matrix form, that is, in rows and columns. Each row of subpixels can include a plurality of subpixels arranged in a second direction, and each column of subpixels can include a plurality of subpixels arranged in the first direction that intersects the second direction.

[0342] It should be noted that the next adjacent subpixel in the first direction may only be a next adjacent subpixel to Petition 870260037267, dated 04 / 22 / 2026, page 113 / 259 109 / 112 seventh transistor T7 in the same column.

[0343] When the subpixel and its subpixel drive circuit have the structures mentioned above, this is able to effectively reduce the layout space occupied by the subpixel drive circuit in order to ensure the operating performance of the subpixel drive circuit, and increase the resolution of the display substrate.

[0344] The present description also provides in some embodiments a display device that includes the display substrate mentioned above.

[0345] In the display substrate according to the embodiments of the present description, when the second electrode plate Cst2 of the storage capacitor Cst is coupled in the VDD power line pattern, the second electrode plate Cst2 of the storage capacitor Cst can have the same fixed potential as the power transmitted in the VDD power line pattern.Furthermore, when the second electrodes of the two switching transistors are coupled to the first electrode of the driving transistor and the orthogonal projection of the second electrode of at least one of the two switching transistors onto base 50 at least partially overlaps the orthogonal projection of the VDD power line pattern onto base 50, and at least partially overlaps the orthogonal projection of the second electrode plate Cst2 of the storage capacitor Cst onto base 50, such that the second electrode plate Cst2 of the storage capacitor Cst and the VDD power line pattern can shield the second electrode of at least one of the two switching transistors, so as to reduce line crossover to the second electrode of at least one of the two switching transistors due to a signal on the other conductive pattern (e.g., a signal line pattern) surrounding it. Petition 870260037267, dated 04 / 22 / 2026, page 114 / 259 110 / 112 minus one of the two switching transistors, thereby reducing the crossover line to the first electrode of the drive transistor.

[0346] Thus, when the display device includes the aforementioned display substrate, it can have the same beneficial effect, which will not be repeatedly described here.

[0347] The present description further provides in some embodiments a method for fabricating a display substrate, which includes forming a plurality of subpixels on a base in a matrix form. The subpixel includes: a data line pattern extending in a first direction; a power line pattern that includes a portion extending in the first direction; and a subpixel drive circuit. The subpixel drive circuit includes two switching transistors, a drive transistor, and a storage capacitor. A first electrode of the storage capacitor is coupled to a gate electrode of the drive transistor, and a second electrode plate of the storage capacitor is coupled to the power line pattern. The second electrodes of the two switching transistors are coupled to a first electrode of the drive transistor.An orthogonal projection of the second electrode of at least one of the two switching transistors onto the base at least partially overlaps an orthogonal projection of the power supply line pattern onto the base and at least partially overlaps an orthogonal projection of the second electrode plate of the storage capacitor onto the base.

[0348] In the display substrate manufactured using the above method according to the embodiments of the present description, when the second electrode plate Cst2 of the storage capacitor Cst is coupled in the VDD power line pattern, so that the Petition 870260037267, dated 04 / 22 / 2026, page 115 / 259 111 / 112 second electrode plate Cst2 of storage capacitor Cst can have the same fixed potential as the power supply transmitted in the VDD power line pattern. Furthermore, when the second electrodes of the two switching transistors are coupled to the first electrode of the driving transistor, and the orthogonal projection of the second electrode of at least one of the two switching transistors onto base 50 at least partially overlaps the orthogonal projection of the VDD power line pattern onto base 50 and at least partially overlaps the orthogonal projection of the second electrode plate Cst2 of storage capacitor Cst onto base 50, such that the second electrode plate Cst2 of storage capacitor Cst and the VDD power line pattern can shield the second electrode of at least one of the two switching transistors.in order to reduce the crosshair to the second electrode of at least one of the two switching transistors due to a signal on the other conductive pattern (e.g., a signal line pattern) surrounding at least one of the two switching transistors, thereby reducing the crosshair to the first electrode of the driving transistor.

[0349] It should also be appreciated that the above modalities were described in a progressive manner, and the same or similar contents in the modalities were not repeated, that is, each modality merely focused on the difference from the others. Especially, the method modalities are substantially similar to the product modalities and were thus described in a simple manner.

[0350] Unless otherwise defined, any technical or scientific term used herein shall have the common meaning understood by a person skilled in the art. Such words as first and second used in specifications and claims are Petition 870260037267, dated 04 / 22 / 2026, p. 116 / 259 112 / 112 are merely used to differentiate different components rather than to represent any order, number, or importance. Words such as include or comprise are intended to indicate that an element or object before the word contains an element or object or its equivalents listed after the word, without excluding any other element or object. Words such as connect / connected to or couple / coupled to may include an electrical connection, direct or indirect, rather than being limited to a physical or mechanical connection. Words such as over, under, left, and right are merely used to represent a relative positional relationship, and when an absolute position of the object is changed, the relative positional relationship is also changed.

[0351] It should be appreciated that, in the case where such an element as a layer, film, region or substrate is placed on or under another element, the element may be directly placed on or under the other element, or an intermediate element may be placed between them.

[0352] In the description above, the resources, structures, materials or features may be combined in any one or more modalities or examples in an appropriate manner.

[0353] The above are specific implementations of the present description, but the scope of protection of the present description is not limited to this. Anyone skilled in the art may make further modifications and improvements without departing from the principle of the present description, and such modifications and improvements shall also fall within the scope of the present description. The scope of protection of the present description is defined by the claims. Petition 870260037267, dated 04 / 22 / 2026, page 117 / 259

Claims

1 / 7 CLAIMS 1. Display substrate comprising a base (50) and a plurality of subpixels arranged on the base (50) in a matrix form, wherein the subpixel comprises: a data line pattern (DATA1) extending in a first direction; a first shielding member (404), wherein at least a portion of the first shielding member (404) extends in the first direction; a drive transistor (T3), a first transistor (T1), and a second shielding member (301), characterized in that a drain electrode (D1) of the first transistor (T1) is coupled to a gate electrode (203g) of the drive transistor (T3), and the second shielding member (301) is coupled to the first shielding member (404); each of the first shielding member (404) and the second shielding member (301) has a fixed potential;the first transistor (T1) is of a double-gate structure, the first transistor (T1) comprises a fourth semiconductor pattern, a fifth semiconductor pattern and a sixth conductor pattern (101px), the sixth conductor pattern (101px) is coupled to the fourth semiconductor pattern and to the fifth semiconductor pattern, and a second electrode of the drive transistor (T3) is coupled to the fourth semiconductor pattern or to the fifth semiconductor pattern; the second electrode of the drive transistor (T3) is one between the source electrode (S3) of the drive transistor (T3) and the drain electrode (D3) of the drive transistor (T3), and a first electrode of the drive transistor (T3) is the other between the source electrode (S3) of the drive transistor (T3) and the drain electrode (D3) Petition 870260037267, dated 04 / 22 / 2026, page 118 / 259 2 / 7 of the drive transistor (T3);an orthogonal projection of the second shielding member (301) onto the base (50) at least partially overlaps an orthogonal projection of the sixth conductor pattern (101px) onto the base (50); at least part of the first shielding member (404) is located between a second electrode of the drive transistor (T3) and a data line pattern (DATA1) of an adjacent subpixel, and the first shielding member (404) is disposed on one side of the second shielding member (301) distal to the base (50).

2. Display substrate according to claim 1, characterized in that the second shielding member (301) is disposed closer to the base (50) than the first shielding member (404).

3. Display substrate according to claim 2, characterized in that an overlapping area between an orthogonal projection of the first shielding member (404) onto the base (50) and an orthogonal projection of the second electrode of the drive transistor (T3) onto the base (50) is E1, a portion of the orthogonal projection of the second electrode of the drive transistor (T3) onto the base (50) does not overlap the orthogonal projection of the first shielding member (404) onto the base (50), an area of ​​the portion of the orthogonal projection of the second electrode of the drive transistor (T3) onto the base (50) that does not overlap the orthogonal projection of the first shielding member (404) onto the base (50) is E2, and E1 <E2.

4. Display substrate according to claim 1, characterized in that in a second direction, a minimum straight-line distance between the orthogonal projection of the second electrode of the drive transistor (T3) onto the base (50) and the orthogonal projection of the first shielding member (404) onto the base (50) is L1, a minimum straight-line distance between the orthogonal projection of the second electrode of the drive transistor (T3) onto the base (50) and an orthogonal projection of the data line pattern (DATA1) of the adjacent subpixel onto the base (50) is L2, and L1 <L2.

5. Display substrate according to claim 4, characterized in that the length of one channel of the drive transistor (T3) is L3, and L1 <L2<L3.

6. Display substrate according to claim 1, characterized in that a minimum straight-line distance between the second electrode of the drive transistor (T3) and the data line pattern (DATA1) of the adjacent subpixel is L4, a minimum straight-line distance between the second electrode of the drive transistor (T3) and the first shield member (404) is L5, and L5 <L4.

7. Display substrate according to claim 1, characterized in that the subpixel further comprises a connecting line (401), the gate electrode (203g) of the drive transistor (T3) is coupled to a second electrode of the first transistor (T1) via the connecting line (401); the orthogonal projection of the second shielding member (301) onto the base (50) is located between an orthogonal projection of one end of the connecting line (401) coupled to the second electrode of the first transistor (T1) onto the base (50) and the orthogonal projection of the data line pattern (DATA1) of the adjacent subpixel onto the base (50).

8. Display substrate according to claim 7, characterized in that in the first direction, a length of the first shielding member (404) is greater than a length of the connecting line (401).

9. Display substrate according to claim 3, Petition 870260037267, dated 22 / 04 / 2026, page 120 / 259 4 / 7 characterized in that a length of a portion of the second electrode of the drive transistor (T3) that does not overlap the first shielding member (404) in the first direction is L6, a length of the first shielding member (404) in the first direction is L7, and L6 <L7.

10. Display substrate according to claim 1, characterized in that a gap is provided between the orthogonal projection of the first shielding member (404) onto the base (50) and the orthogonal projection of the second electrode of the drive transistor (T3) onto the base (50).

11. Display substrate according to claim 1, characterized in that the subpixel further comprises a fourth transistor, a first electrode of the fourth transistor is coupled to the data line pattern (DATA1), and a second electrode of the fourth transistor is coupled to a first electrode of the drive transistor (T3); the orthogonal projection of the second shielding member (301) onto the base (50) does not overlap an orthogonal projection of a fourth transistor of the adjacent subpixel onto the base (50).

12. Display substrate according to claim 1, characterized in that the first shielding member (404) and the second shielding member (301) are configured to receive a first fixed potential signal.

13. Display substrate according to claim 12, characterized in that the subpixel further comprises a storage capacitor (Cst), the storage capacitor (Cst) comprising a first electrode plate (Cst1) and a second electrode plate (Cst2), the first electrode plate (Cst1) is coupled to the gate electrode (203g) of the drive transistor (T3), the second electrode plate (Cst2) is configured to receive a second fixed potential signal; a gap is provided between an orthogonal projection of the second electrode plate (Cst2) onto the base (50) and the orthogonal projection of the first shielding member (404) onto the base (50); the orthogonal projection of the second electrode of the drive transistor (T3) onto the base (50) comprises a portion within the gap.

14. Display substrate according to claim 13, characterized in that the first fixed potential signal is the same as the second fixed potential signal.

15. Display substrate according to claim 2, characterized in that the second electrode of the drive transistor (T3) is disposed closer to the base (50) than the first shielding member (404) and the second shielding member (301).

16. Display substrate according to claim 1, characterized in that an active layer of the first transistor (T1) is arranged in the same layer as, and integrally formed with, an active layer of the drive transistor (T3).

17. Display substrate according to claim 1, characterized in that a minimum straight-line distance between the first shielding member (404) and the second electrode of the drive transistor (T3) is greater than a minimum straight-line distance between the second shielding member (301) and the sixth conductor pattern (101px).

18. Display substrate according to claim 1, characterized in that the subpixel further comprises: a reset signal line pattern (RST1) and a startup signal line pattern (VINT1), wherein each of the reset signal line pattern (RST1) and the startup signal line pattern (VINT1) extends in a second direction that intersects the first direction; a second transistor (T2), wherein a gate electrode (202g) of the second transistor (T2) is coupled to the reset signal line pattern (RST1), a first electrode (S2) of the second transistor (T2) is coupled to the initialization signal line pattern (VINT1), and a second electrode (D2) of the second transistor (T2) is coupled to the gate electrode (203g) of the drive transistor (T3).

19. Display substrate according to claim 18, characterized in that an orthogonal projection of a contact portion of the second shielding member (301) in contact with the first shielding member (404) on the base (50) does not overlap an orthogonal projection of an active layer of the second transistor (T2) on the base (50); a distance between the contact portion and the sixth conductor pattern (101px) is less than a distance between the contact portion and the second electrode of the drive transistor (T3); a distance between the orthogonal projection of the contact portion on the base (50) and the orthogonal projection of the sixth conductor pattern (101px) on the base (50) is less than a distance between the orthogonal projection of the contact portion on the base (50) and the orthogonal projection of the data line pattern (DATA1) on the base (50).

20. Display substrate according to claim 18, characterized in that the subpixel further comprises: a light emission control signal line pattern (EM) and a power line pattern (VDD), wherein the light emission control signal line pattern (EM) extends in the second direction, the power line pattern (VDD) comprises a portion extending in the first direction; a fifth transistor (T5), wherein a gate electrode (205g) of the fifth transistor (T5) is coupled to the light emission control signal line pattern (EM), a first electrode of the fifth transistor (T5) is coupled to the power line pattern (VDD), and a second electrode of the fifth transistor (T5) is coupled to the first electrode of the drive transistor (T3).

21. Display substrate according to claim 20, characterized in that the subpixel further comprises a light-emitting element and a sixth transistor (T6), a gate electrode (205g) of the sixth transistor (T6) is coupled to the light-emitting (EM) control signal line pattern, a first electrode of the sixth transistor (T6) is coupled to the second electrode of the drive transistor (T3), and a second electrode of the sixth transistor (T6) is coupled to the light-emitting element.

22. Display device, characterized in that it comprises the display substrate as defined in any one of claims 1 to 21. Petition 870260037267, dated 04 / 22 / 2026, pp. 124 / 259

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