SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING IT

Description

1 / 63 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING IT

[001] The present disclosure claims priority from Patent Application No. CH 202311728460.1, filed with the China National Intellectual Property Administration on December 14, 2023, and entitled “SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREFOR”, which is incorporated herein by reference in its entirety. FIELD OF TECHNIQUE

[002] The embodiments of the present disclosure relate to the field of semiconductor technologies and, in particular, to a semiconductor structure and a method of manufacturing the same. BACKGROUND

[003] With technological advances, the integration and consolidation of semiconductor packages have been gradually improved, and electronic devices are developing towards miniaturization, high speed, high reliability, low cost, and low power consumption, and high-bandwidth memory (HBM) products are lacking. To realize high-capacity HBMs, a wafer-on-wafer (WoW) packaging technology or a chip-on-chip (CoC) packaging technology is required.

[004] However, in a semiconductor packaging technology, secondary processing is required after the wafer-level test. To ensure a flat bonding interface, it is often necessary to achieve flatness by depositing a thick dielectric layer several times, as well as chemical polishing. Petition 870240107010, dated 12 / 16 / 2024, page 12 / 170 2 / 63 mechanical, and based on this, the dielectric layer is subjected to a deep hole or Damascus etching process. The process is more complex, and deep hole etching is prone to metal-to-metal contact problems caused by excessive byproducts. SUMMARY

[005] Embodiments of the present disclosure provide a semiconductor structure and a method of fabrication thereof, which at least helps to improve the electrical performance of the semiconductor structure.

[006] According to some embodiments of the present disclosure, one aspect of the embodiments of the present disclosure provides a semiconductor structure, including: a first substrate and a semiconductor device located on the first substrate; multiple first conductive pads, connected to the semiconductor device; multiple second conductive pads, at least one of the first conductive pads and at least one of the second conductive pads being electrically connected through a first conductive interconnection structure extending in a direction perpendicular to the first substrate;and a filler layer, the filler layer being filled on the outer periphery of each of the first conductive pads, of the first conductive interconnection structure and of each of the second conductive pads, wherein the first conductive interconnection structure has a surface buried by the filler layer between adjacent conductive pads.

[007] In some embodiments, the filler layer includes a first dielectric layer, a second dielectric layer and a third dielectric layer, the Petition 870240107010, dated 12 / 16 / 2024, page 13 / 170 3 / 63 The first dielectric layer covers the first conductive cushion, the third dielectric layer covers a side wall of the second conductive cushion, the second dielectric layer is located between the first dielectric layer and the third dielectric layer, there is a first predetermined height difference between the upper surface of the second dielectric layer and the upper surface of the first conductive interconnection structure, and the range of the first predetermined height difference is from 0 nm to 50 nm.

[008] In some embodiments, the first dielectric layer and the second dielectric layer constitute a filler sublayer; and the filler layer additionally includes a fourth dielectric layer and the fourth dielectric layer is located between the filler sublayer and the first conductive interconnection structure.

[009] In some embodiments, at least one of the second conductive pads is located on the upper surface of the second dielectric layer.

[0010] In some embodiments, the second conductive pad located on the upper surface of the second dielectric layer is not electrically connected to the first conductive pad, and the second conductive pad is in direct contact with the upper surface of the second dielectric layer.

[0011] In some embodiments, at least one of the first conductive pads in electrical contact with the first conductive interconnection structure includes a first portion and a second portion, the second portion is in direct contact with the first conductive interconnection structure, the first portion is not in direct contact with the first conductive interconnection structure, and the surface of Petition 870240107010, dated 12 / 16 / 2024, page 14 / 170 4 / 63 The second portion in direct contact with the first conductive interconnection structure has a smaller surface area than the first portion.

[0012] In some embodiments, orthographic projections of at least two of the first conductive pads on the first substrate overlap with an orthographic projection of a first conductive interconnect structure on the first substrate.

[0013] In some embodiments, the filling layer includes a first bonding layer, at least one of the second conductive pads has an exposed top surface in the first bonding layer, there is a second predetermined height difference between the top surface of at least one of the second conductive pads exposed in the first bonding layer and the top surface of the first bonding layer, and a range of the second predetermined height difference is from 0 nm to 50 nm.

[0014] In some embodiments, the semiconductor structure additionally includes a second bonding layer and a plurality of third conductive pads located in the second bonding layer, wherein the second bonding layer is directly bonded to the first bonding layer and the third conductive pad is directly bonded to the second conductive pads.

[0015] In some embodiments, the semiconductor structure additionally includes an insulation layer, with the insulation layer located in the fill layer between adjacent conductive pads.

[0016] According to some modalities of the present disclosure, another aspect of the modalities of the present Petition 870240107010, dated 12 / 16 / 2024, p. 15 / 170 5 / 63 disclosure further provides a fabrication method for a semiconductor structure, which includes: providing a first substrate, the first substrate that has a semiconductor device; forming multiple first conductive pads connected to the semiconductor device; forming a first aperture, wherein the first aperture exposes the surface of at least one of the first conductive pads; forming a first conductive interconnect structure that fills the first aperture; and forming multiple second conductive pads on the first conductive interconnect structure, such that at least one of the first conductive pads and at least one of the second conductive pads are electrically connected through the first conductive interconnect structure;wherein a filling layer is formed on the outer periphery of each of the first conductive pads, each of the second conductive pads, and the first conductive interconnection structure, and the first conductive interconnection structure has a surface buried by a filling layer between adjacent second conductive pads.

[0017] In some embodiments, the filling layer includes a first dielectric layer, a second dielectric layer, and a third dielectric layer; the first conductive pads are formed in the first dielectric layer; the second dielectric layer is formed above the first dielectric layer; the first dielectric layer and the second dielectric layer are formed before the first opening is formed; and the first opening is formed in the first dielectric layer and the second dielectric layer after the first conductive interconnection structure is formed. Petition 870240107010, dated 12 / 16 / 2024, page 16 / 170 6 / 63 In the first opening, the leveling process is performed on the surface of the first conductive interconnection structure, so that a first predetermined height difference exists between the upper surface of the second dielectric layer and the upper surface of the first conductive interconnection structure, wherein the range of the first predetermined height difference is from 0 nm to 50 nm; and after the first conductive interconnection structure is formed, the third dielectric layer is formed and the second electrically connected conductive cushions to the first conductive interconnection structure are formed in the third dielectric layer.

[0018] In some embodiments, the filling layer additionally includes a fourth dielectric layer, the fourth dielectric layer is formed after the first opening is formed and before the first conductive interconnection structure is formed, so that the fourth dielectric layer is located between the first conductive interconnection structure and both the first dielectric layer and the second dielectric layer.

[0019] In some embodiments, the fourth dielectric layer formation step includes: forming an initial fourth dielectric layer, wherein the initial fourth dielectric layer conformably covers the surface of the first opening and the upper surface of the second dielectric layer; and corroding the initial fourth dielectric layer to remove the initial fourth dielectric layer located on the upper surface of the second dielectric layer and on the lower part of the first opening, wherein the remaining initial fourth dielectric layer is the fourth dielectric layer, wherein in the corrosion step of Petition 870240107010, dated 12 / 16 / 2024, page 17 / 170 7 / 63 fourth initial dielectric layer, a partial thickness of the first conductive cushion exposed by the first opening is corroded.

[0020] In some embodiments, the filling layer additionally includes a first bonding layer, at least one of the second conductive pads has an exposed top surface in the first bonding layer, a second predetermined height difference exists between the top surface of at least one of the second conductive pads exposed in the first bonding layer and the top surface of the first bonding layer, and a range of the second predetermined height difference is from 0 nm to 50 nm; and after the formation of the second conductive pad, the method additionally includes: forming a second bonding layer directly bonded to the first bonding layer and a third conductive pad directly bonded to the second conductive pad.

[0021] The solutions of the technique provided in the embodiments of the present disclosure have at least the following advantages:

[0022] An electrical signal in a semiconductor device is transferred to another electrical device through a first conductive pad, a first conductive interconnect structure, and a second conductive pad, or an electrical signal in another electrical device is transferred to a semiconductor device through a second conductive pad, a first conductive interconnect structure, and a first conductive pad. Based on this, the first conductive pad is primarily configured to implement an electrical connection with the semiconductor device, the second conductive pad is primarily configured to implement Petition 870240107010, dated 12 / 16 / 2024, page 18 / 170 8 / 63 an electrical connection with another electrical device and the first conductive interconnection structure is configured primarily to implement an electrical connection between the first conductive pad and the second conductive pad.

[0023] Based on this, the first conductive interconnect structure has a surface buried by a filler layer between adjacent conductive pads. In other words, orthographic projections of at least two second conductive pads onto a first substrate are projected to overlap an orthographic projection of a first conductive interconnect structure onto the first substrate, so that a first conductive interconnect structure is in electrical contact with at least two second conductive pads. On the one hand, the transmission efficiency of an electrical signal in the first conductive pad, in the first conductive interconnect structure, and in the second conductive pad is improved.On the other hand, in the horizontal direction, the length of the first conductive interconnection structure is greater than the length of the second conductive cushion, which helps to improve the alignment accuracy between the second conductive cushion and the first conductive interconnection structure. This increases the contact area between the second conductive cushion and the first conductive interconnection structure, thus reducing contact resistance between the second conductive cushion and the first conductive interconnection structure, which additionally improves the efficiency of electrical signal transfer. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] One or more modalities are exemplified Petition 870240107010, dated 12 / 16 / 2024, page 19 / 170 9 / 63 with the Figures in the attached drawings corresponding to one or more embodiments. These example descriptions are not intended to limit the embodiments. Elements with the same reference numerals in the attached drawings are similar elements and, unless specifically indicated, no scale limitation is imposed by the Figures in the attached drawings. To describe the technical solutions in the embodiments of the present disclosure or conventional technologies more clearly, the attached drawings required by the embodiments are briefly described below. Clearly, the attached drawings in the following description show only some embodiments of the present disclosure and other drawings can be obtained by a person of ordinary skill in the art from these attached drawings without creative effort.

[0025] Figure 1 is a schematic cross-sectional structural diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0026] Figure 2 is a schematic cross-sectional structural diagram of a first conductive interconnect structure and a filler layer in a semiconductor structure according to an embodiment of the present disclosure;

[0027] Figure 3 is another schematic cross-sectional structural diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0028] Figure 4 is yet another schematic cross-sectional structural diagram of a semiconductor structure according to an embodiment of the present invention. Petition 870240107010, dated 12 / 16 / 2024, page 20 / 170 10 / 63 revelation;

[0029] Figure 5 is yet another schematic cross-sectional structural diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0030] Figure 6 is a schematic cross-sectional structural diagram of a second conductive cushion and a filler layer in a semiconductor structure according to an embodiment of the present disclosure;

[0031] Figure 7 is another schematic cross-sectional structural diagram of a second conductive cushion and a filler layer in a semiconductor structure according to an embodiment of the present disclosure;

[0032] Figure 8 is yet another schematic cross-sectional structural diagram of a semiconductor structure according to an embodiment of the present disclosure;

[0033] Figure 9 is a schematic cross-sectional structural diagram corresponding to each step in a fabrication method for a semiconductor structure;

[0034] Figure 10 is a schematic flowchart corresponding to a manufacturing method for a semiconductor structure according to another embodiment of the present disclosure; and

[0035] Figures 11 to 27 are schematic cross-sectional structural diagrams corresponding to each step of a fabrication method for a semiconductor structure according to another embodiment of the present disclosure. DESCRIPTION OF MODALITIES Petition 870240107010, dated 12 / 16 / 2024, page 21 / 170 11 / 63

[0036] It can be deduced from the context that the electrical performance of a semiconductor structure needs to be improved.

[0037] The present disclosure provides a semiconductor structure and a method of fabrication thereof. In the semiconductor structure, a first conductive pad is primarily configured to implement an electrical connection to a semiconductor device, a second conductive pad is primarily configured to implement an electrical connection to another electrical device, and a first conductive interconnect structure is primarily configured to implement an electrical connection between the first conductive pad and the second conductive pad. Based thereon, the first conductive interconnect structure has a surface buried by a filler layer between adjacent conductive pads.In other words, orthographic projections of at least two second conductive pads onto a first substrate are projected to overlap an orthographic projection of a first conductive interconnect structure onto the first substrate, such that a first conductive interconnect structure is in electrical contact with at least two second conductive pads. On the one hand, the transmission efficiency of an electrical signal in the first conductive pad, the first conductive interconnect structure, and the second conductive pad is improved. On the other hand, in the horizontal direction, the length of the first conductive interconnect structure is greater than the length of the second conductive pad, which helps to improve the alignment accuracy between the second conductive pad and the first conductive interconnect structure, thus increasing... Petition 870240107010, dated 12 / 16 / 2024, page 22 / 170 12 / 63 Thus, a contact area is created between the second conductive pad and the first conductive interconnect structure, in order to reduce contact resistance between the second conductive pad and the first conductive interconnect structure, which further improves the efficiency of electrical signal transfer.

[0038] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. However, it may be understood by a person of ordinary skill in the art that in the embodiments of the present disclosure, many technical details are provided to enable readers to better understand the embodiments of the present disclosure. However, the solutions of the art claimed in the embodiments of the present disclosure can be implemented even without these technical details and various alterations and modifications made based on the following embodiments.

[0039] One embodiment of the present disclosure provides a semiconductor structure. The semiconductor structure provided in one embodiment of the present disclosure is described in detail below with reference to the accompanying drawings. It should be noted that, for ease of description and a clear indication of a feature of a semiconductor structure, Figures 1 to 8 in one embodiment of the present disclosure are all schematic local structural diagrams of the semiconductor structure.

[0040] With reference to Figure 1, Figure 1 is a schematic cross-sectional structural diagram of a semiconductor structure according to an embodiment of the present disclosure. The semiconductor structure includes a first substrate 100 and a semiconductor device (not Petition 870240107010, dated 12 / 16 / 2024, p. 23 / 170 13 / 63 shown in the Figure) located on the first substrate 100; multiple first conductive pads 101, connected to the semiconductor device; multiple second conductive pads 105, at least one of the first conductive pads 101 and at least one of the second conductive pads 105 that is electrically connected through a first conductive interconnect structure 103 that extends in a direction X perpendicular to the first substrate 100; and a fill layer 142, wherein the fill layer 142 is filled on the outer periphery of each of the first conductive pads 101, of the first conductive interconnect structure 103 and of each of the second conductive pads 105, wherein the first conductive interconnect structure 103 has a surface 103b buried by the fill layer 142 between adjacent conductive pads 105.In some cases, an electrical signal in the semiconductor device is transferred to another electrical device through the first conductive pad 101, the first conductive interconnect structure 103, and the second conductive pad 105, or an electrical signal in another electrical device is transferred to the semiconductor device through the second conductive pad 105, the first conductive interconnect structure 103, and the first conductive pad 101. Based on this, the first conductive pad 101 is primarily configured to implement an electrical connection with the semiconductor device, the second conductive pad 105 is primarily configured to implement an electrical connection with another electrical device, and the first conductive interconnect structure 103 is primarily configured to implement an electrical connection between the first conductive pad 101 and the second pad. Petition 870240107010, dated 12 / 16 / 2024, page 24 / 170 14 / 63 conductive 105.

[0041] Furthermore, the first conductive interconnect structure 103 has a surface 103b buried by a filling layer 142 between adjacent conductive pads 105, such that orthographic projections of at least two conductive pads 105 on the first substrate 100 overlap with an orthographic projection of the same first conductive interconnect structure 103 on the first substrate 100 and a first conductive interconnect structure 103 is in electrical contact with at least two conductive pads 105. Based on this, a first conductive interconnect structure 103 connected to at least two adjacent conductive pads 105 at the same time is designed. On the one hand, such a design helps to improve the transmission efficiency of an electrical signal in the first conductive pad 101, in the first conductive interconnect structure 103 and in the second conductive pad 105.On the other hand, in the horizontal Y direction, the length of the first conductive interconnect structure 103 is greater than the length of a single second conductive cushion 105, which helps to improve the alignment accuracy between the second conductive cushion 105 and the first interconnect structure 103. Additionally, the single second conductive cushion 105 is in electrical contact with the first conductive interconnect structure 103 as a whole, so that the contact area between the second conductive cushion 105 and the first conductive interconnect structure 103 is increased, to reduce the contact resistance between the second conductive cushion 105 and the first conductive interconnect structure 103, further improving the efficiency of electrical signal transfer. Petition 870240107010, dated 12 / 16 / 2024, page 25 / 170 15 / 63

[0042] It should be noted that, referring to Figure 1, the direction perpendicular to the first substrate 100 is the vertical direction X. In some cases, the vertical direction X may also be the direction in which the first conductive pad 101 points towards the second conductive pad 105. The horizontal direction Y may be perpendicular to the vertical direction X. Furthermore, in Figure 1, for example, a first conductive interconnect structure 103 is in electrical contact with three second conductive pads 105, two second conductive pads 105 are in electrical contact with the first conductive interconnect structure 103 as a whole, and a partial region of the remaining conductive pad 105 is in electrical contact with the first conductive interconnect structure 103.In actual application, firstly, for any second conductive pad 105 in electrical contact with the first conductive interconnect structure 103, the contact area between the second conductive pad 105 and the first conductive interconnect structure 103 is not limited, i.e., the entire region of the second conductive pad 105 may be in electrical contact with the first conductive interconnect structure 103, or a partial region of the second conductive pad 105 may be in electrical contact with the first conductive interconnect structure 103. Secondly, the number of second conductive pads 105 in electrical contact with the same first conductive interconnect structure 103 is not limited, provided that at least two are met.

[0043] In some embodiments, referring to Figure 1, the semiconductor structure may additionally include an insulating layer 151 and at least one portion Petition 870240107010, dated 12 / 16 / 2024, page 26 / 170 16 / 63 of the insulation layer 151 is located in the filling layer 142 between adjacent conductive pads 101. In this way, an insulation effect between the first adjacent conductive pads 101 is improved through an insulation layer 151 whose dielectric constant is lower than the dielectric constant of the filling layer 142, and signal interference in the first adjacent conductive pads 101 is avoided.

[0044] In some forms, the insulation layer 151 may be an air gap.

[0045] In some embodiments, referring to Figure 1 and Figure 2, the filling layer 142 includes a first dielectric layer 122, a second dielectric layer 132 and a third dielectric layer 124, the first dielectric layer 122 covers the first conductive cushion 101, the third dielectric layer 124 surrounds the side wall of the second conductive cushion 105, the second dielectric layer 132 is located between the first dielectric layer 122 and the third dielectric layer 124, there is a first predetermined height difference H1 between the upper surface 132a of the second dielectric layer 132 and the upper surface 103a of the first conductive interconnect structure 103 and the range of the first predetermined height difference H1 is from 0 nm to 50 nm.

[0046] Figure 2 is a schematic cross-sectional structural diagram of a first conductive interconnect structure and a filler layer in a semiconductor structure according to an embodiment of the present disclosure. In some cases, referring to Figure 1, the first predetermined height difference H1 may be 0 Petition 870240107010, dated 12 / 16 / 2024, p. 27 / 170 17 / 63 nm, that is, the upper surface 132a of the second dielectric layer 132 is level with the upper surface 103a of the first conductive interconnect structure 103. In other cases, referring to Figure 2, the upper surface 103a of the first conductive interconnect structure 103 is a concave surface recessed in a direction closer to the first substrate 100 (referring to Figure 1). In this case, the first predetermined height difference H1 is greater than 0 nm and less than or equal to 50 nm. In some other cases, the upper surface of the first conductive interconnect structure may alternatively be a convex surface projecting in a direction away from the first substrate. In this case, the first predetermined height difference H1 is greater than 0 nm and less than or equal to 50 nm.

[0047] It should be noted that, in one embodiment of the present disclosure, it is only defined that the first predetermined height difference H1 exists between the upper surface 132a of the second dielectric layer 132 and the upper surface 103a of the first conductive interconnect structure 103. However, based on the first substrate 100, the height difference between the upper surface 132a of the second dielectric layer 132 and the upper surface 103a of the first conductive interconnect structure 103 is not limited and can be adjusted according to an actual situation.

[0048] Furthermore, in Figure 2, the first predetermined height difference H1 between the upper surface 132a of the second dielectric layer 132 and the upper surface 103a of the first conductive interconnection structure 103 is defined as the maximum vertical distance between each point on the upper surface 132a of the second dielectric layer. Petition 870240107010, dated 12 / 16 / 2024, page 28 / 170 18 / 63 132 and each point on the upper surface 103a of the first conductive interconnection structure 103 in the vertical direction X. Furthermore, the surface 103b of the first conductive interconnection structure 103 buried by the filling layer 142 between adjacent conductive cushions 105 is a portion of the upper surface 103a of the first conductive interconnection structure 103.

[0049] In some embodiments, referring to Figure 1, the filling layer 142 includes a first dielectric layer 122 covering the first conductive pad 101, a third dielectric layer 124 covering the side wall of the second conductive pad 105, and a second dielectric layer 132 located between the first dielectric layer 122 and the third dielectric layer 124. Based on this, the insulation layer 151 is located on the first dielectric layer 122, i.e., the first dielectric layer 122 has the insulation layer 151. It should be noted that, in actual application, the insulation layer may additionally be located on the second dielectric layer.

[0050] In some embodiments, referring to Figure 1, the first dielectric layer 122 and the second dielectric layer 132 constitute a subfilling layer 102. The filling layer 142 may additionally include a fourth dielectric layer 106 and the fourth dielectric layer 106 is located between the subfilling layer 102 and the first conductive interconnection structure 103.

[0051] In some cases, during the formation stage of the first conductive interconnect structure 103, a first opening that accommodates the first conductive interconnect structure 103 needs to be formed in the sub-filling layer. Petition 870240107010, dated 12 / 16 / 2024, page 29 / 170 19 / 63 102 and the fourth dielectric layer 106 is used to protect the side wall of the first opening, so as to prevent corrosion of the sub-filling layer 102 forming the side wall of the first opening, so that the side wall of the first opening has a relatively flat interface, so that the first conductive interconnection structure 103 with a regular size is subsequently formed.

[0052] In some embodiments, referring to Figure 3, Figure 3 is another schematic cross-sectional structural diagram of a semiconductor structure according to an embodiment of the present disclosure. At least one second conductive cushion 105 is located on the upper surface 132a of the second dielectric layer 132. In some examples, at least one second conductive cushion 105 may be in contact with the upper surface 132a of the second dielectric layer 132. In some other embodiments, at least one second conductive cushion 105 may not be in direct contact with the upper surface 132a of the second dielectric layer 132.

[0053] It should be noted that the second conductive pad 105 in contact with the upper surface 132a of the second dielectric layer 132 is not electrically connected to the first conductive pad 101. Additionally, the second conductive pad 105 in contact with the upper surface 132a of the second dielectric layer 132 may not be electrically connected to the semiconductor device, i.e., the second conductive pad 105 in contact with the upper surface 132a of the second dielectric layer 132 may not transfer an electrical signal.

[0054] In this case, on the one hand, if the second conductive cushion 105 is attached to a film layer structure Petition 870240107010, dated 12 / 16 / 2024, page 30 / 170 20 / 63 external, the external film layer structure includes another conductive pad, signal transfer is carried out between some other conductive pads and the second conductive pad 105 in electrical contact with the first conductive interconnect structure 103, but there is another conductive pad remaining in the external film layer structure, the second conductive pad 105 in contact with the upper surface 132a of the second dielectric layer 132 is designed to balance the density distribution of the conductive pads in the external film layer structure and the density distribution of the second conductive pads 105 in the third dielectric layer 124, so that when the second conductive pad 105 is connected to the external film layer structure, two contacting interfaces are affected by a similar degree of thermal expansion, which thus improves,The bonding resistance between the second conductive pad 105 and the outer film layer structure, to improve the contact performance between the second conductive pad 105 and the outer film layer structure.

[0055] On the other hand, if the second conductive cushion 105 is attached to an outer film layer structure, the coefficient of thermal expansion of the outer film layer structure is different from the overall coefficient of thermal expansion of the second conductive cushion 105 and the third dielectric layer 124. The second conductive cushion 105 in contact with the upper surface 132a of the second dielectric layer 132 is designed to help adjust the density distribution of the second conductive cushions 105 in the third dielectric layer 124, so that when the second conductive cushion 105 is attached to the outer film layer structure, two Petition 870240107010, dated 12 / 16 / 2024, page 31 / 170 21 / 63 contacting interfaces are affected by a similar degree of thermal expansion, which thus improves the bonding strength between the second conductive pad 105 and the outer film layer structure, to improve the contact performance between the second conductive pad 105 and the outer film layer structure.

[0056] In some embodiments, referring to Figure 1, the first conductive cushion 101 in electrical contact with the first conductive interconnection structure 103 includes a first portion 111 and a second portion 121, the second portion 121 is in direct contact with the first conductive interconnection structure 103, the first portion 111 is not in direct contact with the first conductive interconnection structure 103 and the surface of the second portion 121 in direct contact with the first conductive interconnection structure 103 has a smaller portion than the surface of the first portion 111.

[0057] In some cases, the upper surface 100a of the first substrate 100 is used as a reference and the upper surface 121a of the second portion 121 is lower than the upper surface 111a of the first portion 111.

[0058] The correspondence between the first conductive cushion 101 and the first conductive interconnection structure 103 includes at least the following two embodiments:

[0059] In some embodiments, referring to Figure 1 or Figure 3, an orthographic projection of only a first conductive cushion 101 onto the first substrate 100 overlaps with an orthographic projection of a first conductive interconnect structure 103 onto the first substrate 100, that is, the first conductive cushion 101 and the first conductive interconnect structure 103 are in a relationship Petition 870240107010, dated 12 / 16 / 2024, p. 32 / 170 22 / 63 one to one.

[0060] It should be noted that in both Figures 1 and 3, for example, in the horizontal Y direction, the length of the first conductive cushion 101 is greater than the length of the first conductive cushion 101 in electrical contact with the first conductive interconnection structure 103. In the actual application, when the first conductive cushion 101 and the first conductive interconnection structure 103 are in a one-to-one relationship, the size ratio between the first conductive cushion 101 and the first conductive interconnection structure 103 in the horizontal Y direction is not limited.

[0061] In some cases, when the first conductive cushion 101 and the first conductive interconnect structure 103 are in a one-to-one relationship, the first conductive cushion 101 may be a wiring layer and the wiring layer may be located in a peripheral region of the semiconductor structure. With reference to Figure 3, the first conductive cushion 101 includes a first wiring layer 131 and a second wiring layer 141. In the Y-length direction, a first length L1 of the first wiring layer 131 is greater than a second length L2 of the second wiring layer 141.

[0062] It should be noted that the first wiring layer 131 and the second wiring layer 141 in the first conductive pad 101 can be considered as the same layer structure, i.e., both are located in a film layer strip in which the first conductive pad 101 is located. However, the first wiring layer 131 and the second wiring layer 141 can be insulated from each other in order to implement an electrical connection between them. Petition 870240107010, dated 12 / 16 / 2024, page 33 / 170 23 / 63 unused conductive structures. Furthermore, in addition to the first wiring layer 131 and the second wiring layer 141, the first conductive cushion 101 may additionally include a third wiring layer, a fourth wiring layer, a fifth wiring layer, or something similar. Furthermore, the first wiring layer 131 and the second wiring layer 141 may be integrally formed, i.e., except for implementing different functions, for example, electrically connected to different semiconductor devices, the first wiring layer 131 and the second wiring layer 141 have the same film structure and material. In Figure 3, the first wiring layer 131 and the second wiring layer 141 are drawn in the same filling manner.

[0063] In some embodiments, still referring to Figure 3, in the horizontal Y direction, the first wiring layer 131 and the second wiring layer 141 may additionally have an insulation layer 151 between them. For example, the first dielectric layer 122 has an insulation layer 151, which helps to improve an insulation effect between the first wiring layer 131 and the second wiring layer 141 through the insulation layer 151.

[0064] In some embodiments, referring to Figure 4, Figure 4 is yet another schematic cross-sectional structural diagram of a semiconductor structure according to an embodiment of the present disclosure. In some embodiments, the first conductive cushion 101 includes a barrier layer 161 and a conductive layer 171. In the vertical X direction, the conductive layer 171 has opposite sides first and second, and the barrier layer 161 covers at least the first and second sides. Petition 870240107010, dated 12 / 16 / 2024, p. 34 / 170 24 / 63

[0065] It can be understood that the barrier layer 161 is configured to prevent conductive ions in the conductive layer 171 from diffusing and migrating to the subfill layer 102, so as to avoid a decrease in the conductive performance of the conductive layer 171 due to the diffusion and migration of conductive ions and to avoid a decrease in the insulation performance of the subfill layer 102 due to the migration of conductive ions, thus ensuring a relatively high conductivity of the conductive layer 171 and a relatively high insulation performance of the subfill layer 102.

[0066] It should be noted that, with reference to Figure 3 and Figure 4, both the first wiring layer 131 and the second wiring layer 141 may include a barrier layer 161 and a conductive layer 171. In actual application, the first conductive pad 101 may alternatively include only the conductive layer 171.

[0067] In some embodiments, the barrier layer material 161 is at least one of titanium or titanium nitride and the conductive layer material 171 is aluminum. In this way, the barrier layer 161 helps to prevent the electromigration of aluminum ions.

[0068] In some other embodiments, referring to Figure 5, Figure 5 is yet another schematic cross-sectional structural diagram of a semiconductor structure according to an embodiment of the present disclosure. Orthographic projections of at least two first conductive cushions 101 on the first substrate 100 overlap an orthographic projection of a first conductive interconnect structure 103 on the first substrate 100. This Petition 870240107010, dated 12 / 16 / 2024, p. 35 / 170 25 / 63 form, a first conductive interconnect structure 103 is in electrical contact with at least two first conductive pads 101. On the one hand, the transmission efficiency of an electrical signal in the first conductive pad 101, in the first conductive interconnect structure 103 and in the second conductive pad 105 is improved. On the other hand, in the horizontal Y direction, the length of the first conductive interconnect structure 103 is greater than the length of a single first conductive pad 101, which helps to improve the alignment accuracy between the first conductive pad 101 and the first conductive interconnect structure 103.Furthermore, the single first conductive pad 101 is in electrical contact with the first conductive interconnect structure 103 as a whole, so that the contact area between the first conductive pad 101 and the first conductive interconnect structure 103 is increased, in order to reduce contact resistance between the first conductive pad 101 and the first conductive interconnect structure 103, additionally improving the efficiency of electrical signal transfer.

[0069] In still other embodiments, a first conductive cushion 101 is correspondingly connected to a first conductive interconnection structure 103, so as to independently form a connection path between each first conductive cushion 101 and a corresponding second conductive cushion 105.

[0070] In some cases, when the first conductive pad 101 and the first conductive interconnect structure 103 are in a multiple-to-one relationship, the first conductive pad 101 may be a signal output layer. For example, the signal output layer may be a layer of Petition 870240107010, dated 12 / 16 / 2024, page 36 / 170 26 / 63 I / O signal output, a power signal output layer, or another type of signal output layer.

[0071] In some embodiments, with reference to Figure 1 and Figure 6, or with reference to Figure 1 and Figure 7, the fill layer 142 may additionally include a first bonding layer 134. The second conductive pad 105 has an upper surface 105a exposed in the first bonding layer 134. A second predetermined height difference H2 exists between the upper surface 105a of the second conductive pad 105 exposed in the first bonding layer 134 and the upper surface 134a of the first bonding layer 134, and the range of the second predetermined height difference H2 is from 0 nm to 50 nm.

[0072] In some cases, the third dielectric layer 124 and the first bonding layer 134 together constitute the dielectric layer 104 and the second conductive cushion 105 penetrates the dielectric layer 104 in the vertical X direction.

[0073] In some cases, referring to the second conductive pad D in Figure 1 or Figure 7, the second predetermined height difference H2 (referring to Figure 6) may be 0 nm, i.e., the upper surface 134a of the first bonding layer 134 is flush with the upper surface 105d of a second conductive pad D or the upper surface 105a of the second conductive pad 105 in Figure 1. In some other cases, referring to Figure 7, the upper surface 105e of the second conductive pad E is a concave surface recessed in a direction closer to the first substrate 100 (referring to Figure 1). In this case, the second predetermined height difference H2 (referring to Figure 6) is greater Petition 870240107010, dated 12 / 16 / 2024, p. 37 / 170 27 / 63 that 0 nm and less than or equal to 50 nm. In still other cases, referring to a second conductive cushion F in Figure 6 or Figure 7, the upper surface 105a of the second conductive cushion 105 is a convex surface that projects in a direction away from the first substrate 100 (referring to Figure 1). In this case, the second predetermined height difference H2 (referring to Figure 6) is greater than 0 nm and less than or equal to 50 nm.

[0074] It should be noted that Figure 6 is a schematic cross-sectional structural diagram of a second conductive pad and a filler layer in a semiconductor structure according to an embodiment of the present disclosure. Figure 7 is another schematic cross-sectional structural diagram of a second conductive pad and a filler layer in a semiconductor structure according to an embodiment of the present disclosure. Furthermore, to distinguish three different second conductive pads 105 in Figure 7, the three different second conductive pads 105 in Figure 7 are respectively marked as D, E and F and the upper surfaces 105a of the three different second conductive pads 105 are respectively marked as 105d, 105e and 105f.

[0075] It should be noted that, in one embodiment of the present disclosure, it is only defined that the second predetermined height difference H2 exists between the upper surface 134a of the first bonding layer 134 and the upper surface 105a of the second conductive cushion 105. However, using the first substrate 100 as a reference, the height difference between the upper surface 134a of the first bonding layer 134 and the upper surface 105a of the Petition 870240107010, dated 12 / 16 / 2024, p. 38 / 170 28 / 63 second conductive cushion 105 is not limited and can be adjusted according to the actual situation.

[0076] Furthermore, in Figure 6, the second predetermined height difference H2 between the upper surface 134a of the first bonding layer 134 and the upper surface 105a of the second conductive pad 105 is defined as the maximum vertical distance between each point on the upper surface 134a of the first bonding layer 134 and each point on the upper surface 105a of the second conductive pad 105 in the vertical direction X.

[0077] It should be noted that in Figure 7, only one example is used to describe the different topography of the upper surface 105a of the second conductive pad 105. The topography of the upper surfaces 105a of different second conductive pads 105 in the same semiconductor structure may be the same or may be different, which can be adjusted according to a real situation.

[0078] In some cases, when the first conductive pad 101 is an I / O signal output layer in the horizontal Y direction, the spacing between the first adjacent conductive pads 101 is relatively small and the length of the first conductive pad 101 itself is relatively small, so the spacing between the second adjacent conductive pads 105 corresponding to the first conductive pads 101 is also relatively small and the length of the second conductive pad 105 itself is relatively small. Based on this, a process parameter for preparing the second conductive pad 105 is adjusted and the upper surface 105a of the second conductive pad 105 is designed to be similar to that shown in Figure 6, i.e., Petition 870240107010, dated 12 / 16 / 2024, page 39 / 170 29 / 63 a convex surface that projects in the opposite direction to the first substrate 100 (referring to Figure 1). Therefore, in a case where the length of the second conductive pad 105 in the horizontal Y direction is relatively small, the alignment accuracy of the connection of the second conductive pad 105 subsequently to a conductive pad in an outer film layer structure is improved and the contact area between the second conductive pad 105 and the conductive pad in the outer film layer structure is increased, so as to improve the efficiency of transferring an electrical signal between the two.

[0079] In some embodiments, referring to Figure 4, the fill layer 142 includes a first dielectric layer 122 and a second dielectric layer 132, the first dielectric layer 122 and the second dielectric layer 132 constitute a fill sublayer 102, and the fill sublayer 102 has a first opening that encloses the first conductive interconnection structure 103. The first conductive interconnection structure 103 includes a first diffusion barrier layer 113, which conformably covers the sidewall and the surface of the lower part of the first opening; a first seed layer 123, which conformally covers the sidewall and the surface of the lower part of the first diffusion barrier layer 113; and a first galvanizing layer 133, which fills the remaining portion of the first opening.

[0080] It should be noted that the first diffusion barrier layer 113 is configured to prevent conductive ions in the first seed layer 123 and the first coating layer 133 from diffusing and migrating to the underfill layer 102, so as to avoid a decrease in Petition 870240107010, dated 12 / 16 / 2024, page 40 / 170 30 / 63 conductive performance of the first seed layer 123 and the first coating layer 133 due to diffusion and migration of conductive ions and a decrease in the insulation performance of the underfill layer 102 due to migration of conductive ions. That is, it is guaranteed that the conductive performance of the first seed layer 123 and the first coating layer 133 is relatively high and the insulation performance of the underfill layer 102 is relatively high.

[0081] In some enclosures, the material of the first diffusion barrier layer 113 is at least one of tantalum or tantalum nitride and the material of the first seed layer 123 and the first electroplating layer 133 is copper. In this way, the first diffusion barrier layer 113 helps to prevent the electromigration of copper ions.

[0082] In some embodiments, still referring to Figure 4, the filling layer 142 includes a third dielectric layer 124 and the third dielectric layer 124 has a second opening that surrounds the second conductive cushion 105. The second conductive cushion 105 includes a second diffusion barrier layer 115, which conformably covers the sidewall and the surface of the lower part of the second opening, a second seed layer 125, which conformally covers the sidewall and the surface of the lower part of the second diffusion barrier layer 115 and a second coating layer 135, filling the remaining portion of the second opening.

[0083] It should be noted that the second diffusion barrier layer 115 is configured to prevent conductive ions in the second seed layer 125 and in the second Petition 870240107010, dated 12 / 16 / 2024, page 41 / 170 31 / 63 coating layer 135 diffuse and migrate to the third dielectric layer 124, so as to avoid a decrease in the conductive performance of the second seed layer 125 and the second coating layer 135 due to the diffusion and migration of conductive ions and a decrease in the insulating performance of the third dielectric layer 124 due to the migration of conductive ions. That is, it is guaranteed that the conductivity of the second seed layer 125 and the second coating layer 135 is relatively high and the insulating performance of the third dielectric layer 124 is relatively high.

[0084] In some embodiments, the material of the second diffusion barrier layer 115 is at least one of tantalum or tantalum nitride and the material of the second seed layer 125 and the second electroplating layer 135 is copper. In this way, the second diffusion barrier layer 115 helps to prevent the electromigration of copper ions.

[0085] It should be noted that in Figure 4, the first diffusion barrier layer 113 and the second diffusion barrier layer 115 are drawn in the same filling manner. In actual application, the materials of the first diffusion barrier layer 113 and the second diffusion barrier layer 115 may be the same or different.

[0086] In some embodiments, referring to Figure 8, Figure 8 is yet another schematic cross-sectional structural diagram of a semiconductor structure according to an embodiment of the present disclosure. The semiconductor structure may additionally include a second bonding layer 234 and a third conductive cushion 205 located in the second bonding layer 234. A Petition 870240107010, dated 12 / 16 / 2024, page 42 / 170 32 / 63 second bonding layer 234 is directly bonded to the first bonding layer 134 and the third conductive pad 205 is directly bonded to the second conductive pad 105.

[0087] It should be noted that no adhesive is used for the direct bonding between the second bonding layer 234 and the first bonding layer 134 and the direct bonding between the third conductive pad 205 and the second conductive pad 105 can implement an electrical connection between the two.

[0088] In some embodiments, the third conductive cushion 205 and the second conductive cushion 105 may be in a one-to-one correspondence.

[0089] It should be noted that, in Figure 8, for example, orthographic projections of the third conductive cushion 205 and the second conductive cushion 105 on the first substrate 100 overlap. In actual application, the size ratio between the areas of the orthographic projections of the third conductive cushion 205 and the second conductive cushion 105 on the first substrate 100 is not limited and can be adjusted according to actual need. Furthermore, referring to Figure 4, a film structure within the third conductive cushion 205 is similar to a film structure within the second conductive cushion 105, and details are not described in this document. In other words, the third conductive cushion 205 also includes a diffusion barrier layer, a seed layer, and a galvanization layer.

[0090] In some embodiments, referring to Figure 8, the semiconductor structure may additionally include: a second conductive interconnect structure 203, in which at least one third conductive cushion 205 is in Petition 870240107010, dated 12 / 16 / 2024, page 43 / 170 33 / 63 electrical contact with the same second conductive interconnection structure 203; a second filling layer 242, wherein the second filling layer 242 is filled on the outer periphery and in a strip of each third conductive cushion 205 and the second conductive interconnection structure 203; and a second substrate 200, wherein the second filling layer 242 is located on the second substrate 200.

[0091] It should be noted that, in Figure 8, for example, the three third conductive pads 205 are in electrical contact with the same second conductive interconnection structure 203. In the actual application, the number of third conductive pads 205 in electrical contact with the same second conductive interconnection structure 203 is not limited and can be adjusted according to the actual situation. Furthermore, the third conductive pad 205 is another conductive pad in the outer film structure described in the previous embodiment.

[0092] In some cases, the first substrate 100, the fill layer 142 located on the first substrate 100, and the first conductive pad 101, the first conductive interconnect structure 103, and the second conductive pad 105 located on the fill layer 142 are all components of a first semiconductor chip. The second substrate 200, the second fill layer 242 located on the second substrate 200, and the second conductive interconnect structure 203 and the third conductive pad 205 located on the second fill layer 242 are all components of a second semiconductor chip. The first semiconductor chip and the second semiconductor chip are joined at the first bonding layer 134, and an electrical signal is transferred through a bonding connection between the second Petition 870240107010, dated 12 / 16 / 2024, page 44 / 170 34 / 63 conductor cushion 105 and the third conductor cushion 205.

[0093] It should be noted that, firstly, referring to Figure 4, a film structure within the second conductive interconnect structure 203 is similar to a film structure within the first conductive interconnect structure 103, and the details are not described in this document. In other words, the second conductive interconnect structure 203 also includes a diffusion barrier layer, a seed layer, and a coating layer. Secondly, referring to Figure 4, the film structure within the second fill layer 242 is similar to a film structure within the fill layer 142, and the details are not described in this document. In other words, the second fill layer 242 also includes several dielectric layers. Thirdly, a semiconductor device contained in the second substrate 200 and a semiconductor device contained in the first substrate 100 may be the same or different.If the semiconductor device contained in the second substrate 200 and the semiconductor device contained in the first substrate 100 are the same, then the first semiconductor chip and the second semiconductor chip are of the same type. If the semiconductor device contained in the second substrate 200 and the semiconductor device contained in the first substrate 100 are different, then the first semiconductor chip and the second semiconductor chip are of different types.

[0094] In conclusion, the first conductive pad 101 is primarily configured to implement an electrical connection with the semiconductor device, the second conductive pad 105 is primarily configured to implement an electrical connection with another electrical device, and the Petition 870240107010, dated 12 / 16 / 2024, page 45 / 170 The first conductive interconnect structure 103 is primarily configured to implement an electrical connection between the first conductive pad 101 and the second conductive pad 105. Based on this, it is designed that orthographic projections of at least two second conductive pads 105 onto the first substrate 100 overlap with an orthographic projection of the first conductive interconnect structure 103 onto the first substrate 100, such that a first conductive interconnect structure 103 is in electrical contact with at least two second conductive pads 105. On the one hand, this helps to improve the transmission efficiency of an electrical signal in the first conductive pad 101, the first conductive interconnect structure 103, and the second conductive pad 105.On the other hand, in the horizontal Y direction, the length of the first conductive interconnect structure 103 is greater than the length of a single second conductive cushion 105, which helps to improve the alignment accuracy between the second conductive cushion 105 and the first interconnect structure 103. Additionally, the single second conductive cushion 105 is in electrical contact with the first conductive interconnect structure 103 as a whole, so that the contact area between the second conductive cushion 105 and the first conductive interconnect structure 103 is increased, to reduce the contact resistance between the second conductive cushion 105 and the first conductive interconnect structure 103, further improving the efficiency of electrical signal transfer.

[0095] Another embodiment of the present disclosure further provides a manufacturing method for a semiconductor structure, which is configured to prepare the Petition 870240107010, dated 12 / 16 / 2024, p. 46 / 170 36 / 63 semiconductor structure described in the previous embodiment. The following describes in detail the manufacturing method for a semiconductor structure provided in another embodiment of the present disclosure with reference to the accompanying drawings. It should be noted that a portion equal to or corresponding to the previous embodiment is not described herein again. It was found through analysis that, referring to 9a in Figure 9, to create an electrical connection layer 10 in the semiconductor structure, after the formation of the electrical connection layer 10 and the first insulation layer 11 surrounding the electrical connection layer 10, the first insulation layer 11 is graphically processed so as to form an opening 12 exposing the electrical connection layer 10.During the graphic processing stage, corrosion damage is easily caused to the surface exposed by the electrical connection layer 10, which affects the subsequent electrical connection performance of the electrical connection layer 10 and a conductor pillar.

[0096] It should be noted that 9a to 9d in Figure 9 are each a schematic cross-sectional structural diagram corresponding to each step in a fabrication method for a semiconductor structure.

[0097] With reference to 9a and 9b in Figure 9, a second layer of insulation 13 of a large block is deposited in the opening 12. In the deposition step, due to the existence of the opening 12, there is a relatively large height difference between the second layer of insulation 13 formed on the upper surface of the first layer of insulation 11 and the second layer of insulation 13 formed in the opening 12, i.e., high step.

[0098] With reference to 9b and 9c in Figure 9, chemical-mechanical polishing (CMP) is performed on the second layer. Petition 870240107010, dated 12 / 16 / 2024, page 47 / 170 37 / 63 of insulation 13. A relatively large height difference exists between the second layers of insulation 13 in different regions shown in Figure 9b, which makes chemical-mechanical polishing difficult to obtain a flat surface of the second layer of insulation 13.

[0099] With reference to 9c in Figure 9, graphic processing is performed on the second insulation layer 13 obtained after chemical-mechanical polishing to form a through 14 exposing the electrical connection layer 10. To expose the electrical connection layer 10, the ratio between the depth and width of the through 14 is relatively large, so that in the step of forming the through 14 by corrosion of the second insulation layer 13, the corrosion byproducts formed in the through 14 are not easily removed and thus there is a corrosion residue in the through 14.

[00100] With reference to 9c and 9d in Figure 9, a conductive pillar 15 is formed on the path 14 and it is easy to reduce the conductivity of the conductive pillar 15 due to the existence of the recording residue, i.e., an increase in the overall resistance of the conductive pillar 15. Therefore, it is additionally easy to cause poor contact between the conductive pillar 15 and the electrical connection layer 10.

[00101] With reference to 9d in Figure 9, a third insulation layer 16 is formed and a conductive layer 17 is formed on the third insulation layer 16 by means of a Damascene process.

[00102] It can be learned from the previous description that, to conduct the electrical connection layer 10 in the semiconductor structure, the dielectric layers (e.g., the first insulation layer 11, the second layer Petition 870240107010, dated 12 / 16 / 2024, page 48 / 170 38 / 63 of insulation 13 and the third insulation layer 16) need to be deposited several times, and chemical-mechanical polishing is often necessary to achieve a flat surface. At this stage, the difficulty of chemical-mechanical polishing depends on the uniformity of the insulation layer film formed. Furthermore, based on this, deep hole etching, a Damascus process, and similar techniques are performed on the insulation layer, and the process procedure is relatively complex. Additionally, deep hole etching tends to cause the problem of poor contact between the electrical connection layer 10 and the conductive pillar 15 due to excess byproducts.

[00103] Another embodiment of the present disclosure provides a fabrication method for a semiconductor structure. The following describes in detail the fabrication method for a semiconductor structure provided in another embodiment of the present disclosure with reference to the accompanying drawings. Figure 10 is a schematic flowchart corresponding to a fabrication method for a semiconductor structure according to another embodiment of the present disclosure. Figures 11 to 27 are schematic cross-sectional structural diagrams corresponding to each step of a fabrication method for a semiconductor structure according to another embodiment of the present disclosure. It should be noted that, to facilitate description and clearly show the steps of the fabrication method of a semiconductor structure, Figures 11 to 27 in this embodiment are all schematic local structural diagrams of the semiconductor structure.

[00104] With reference to Figure 10 to Figure 27, a fabrication method for a semiconductor structure includes Petition 870240107010, dated 12 / 16 / 2024, page 49 / 170 39 / 63 the following steps: S101: a first substrate 100 is provided, the first substrate 100 having a semiconductor device and multiple first conductive pads 101 connected to the semiconductor device are formed; S102: a first aperture 112 is formed, the first aperture 112 exposing the surface of at least one of the first conductive pads 101; S103: a first conductive interconnect structure 103 filling the first aperture 112 is formed; S104: multiple second conductive pads 105 are formed on the first conductive interconnect structure 103, such that at least one of the first conductive pads 101 and at least one of the second conductive pads 105 are electrically connected through the first conductive interconnect structure 103.

[00105] A filling layer 142 is formed on the outer periphery of each of the first conductive 'cushions' 101, of each of the second conductive 'cushions' 105 and of the first conductive interconnection structure 103 and the first conductive interconnection structure 103 has a surface 103b buried by a filling layer 142 between adjacent conductive 'cushions' 105 (referring to Figure 1).

[00106] It can be understood that, firstly, after the formation of the first opening 112 exposing the first conductive cushion 101, an insulating layer filling the first opening 112 is no longer formed, so as to avoid the high step problem in a subsequently formed insulating layer and additionally reduce the chemical mechanical polishing step once, thus simplifying a step in the process of preparing a semiconductor structure. In Petition 870240107010, dated 12 / 16 / 2024, page 50 / 170 40 / 63 Second place, the first conductive interconnect structure 103 can be formed in the first opening 112. On the one hand, this helps to increase the contact area between the first conductive interconnect structure 103 and the first conductive cushion 101, so as to reduce the contact resistance between the first conductive interconnect structure 103 and the first conductive cushion 101. On the other hand, the first conductive interconnect structure 103 in contact with and connected to the first conductive cushion 101 does not need to be formed in such a way as to engrave a deep hole, so as to avoid the existence of an engraving byproduct between the first conductive cushion 101 and the first conductive interconnect structure 103 or in the first conductive interconnect structure 103, thus helping to improve the conductivity of the first conductive interconnect structure 103, reducing a contact resistance between the first conductive interconnect structure. 103 and the first conductive cushion 101 and avoiding poor contact between the first conductive interconnection structure 103 and the first conductive cushion 101.

[00107] In some embodiments, still referring to Figures 10 to 27, the filling layer 142 may include a first dielectric layer 122, a second dielectric layer 132, and a third dielectric layer 124. The first conductive cushion 101 is formed in the first dielectric layer 122, the second dielectric layer 132 is formed above the first dielectric layer 122, the first dielectric layer 122 and the second dielectric layer 132 are formed before the first opening 112 is formed, and the first opening 112 is formed in the first dielectric layer 122 and the second dielectric layer 132. Subsequently, how to form the first cushion Petition 870240107010, dated 12 / 16 / 2024, page 51 / 170 41 / 63 conductive 101 is described in detail.

[00108] The following steps in the manufacturing method provided in an embodiment of the present disclosure are described in more detail with reference to the accompanying drawings. With reference to Figure 11 to Figure 18, S101: a first substrate 100 is provided, the first substrate 100 having a semiconductor device; and multiple first conductive pads 101 connected to the semiconductor device are formed. S102: A first aperture 112 is formed, wherein the first aperture 112 exposes the surface of at least one of the first conductive pads 101.

[00109] In some embodiments, the fill layer 142 includes a fill sublayer 102 that surrounds the first conductive pad 101 and the fill sublayer 102 has a first opening 112 that exposes at least a portion of the upper surface of the first conductive pad 101.

[00110] In some embodiments, forming the fill sublayer 102 with the first opening 112 includes the following steps:

[00111] With reference to Figures 11 to 14, a first substrate 100 that does not form a first aperture 112 (referring to Figure 15) includes a first conductive cushion 101 and a subfill layer 102 that encloses the first conductive cushion 101. It should be noted that the subfill layer 102 shown in Figures 11 to 14 encloses each surface of the first conductive cushion 101 and subsequently a first aperture 112 is formed within the subfill layer 102. For ease of description, the reference numeral of the subfill layer after the Petition 870240107010, dated 12 / 16 / 2024, p. 52 / 170 42 / 63 first aperture 112 is formed in Figure 12 to Figure 14 and Figure 15 subsequent to Figure 27 are not distinguishable.

[00112] In some embodiments, referring to Figure 12, the sub-filling layer 102 includes a first dielectric layer 122 and a second dielectric layer 132 that are stacked in the vertical X direction, and the first dielectric layer 122 encloses the first conductive cushion 101. It should be noted that both the first dielectric layer 122 and the second dielectric layer 132 in Figure 12 and subsequent Figure 13 and to Figure 14 are a first dielectric layer and a second dielectric layer before the first opening 112 is formed. For ease of description, the reference numerals of the first dielectric layer and the second dielectric layer after the first opening 112 is formed in Figure 12 to Figure 14 and subsequent Figure 15 to Figure 27 are not distinguished.

[00113] It can be understood that, in addition to the first conductive pad 101, the semiconductor structure includes another semiconductor device, such as a transistor structure, a word line, a bit line, and a capacitor structure. The first dielectric layer 122 and the second dielectric layer 132 jointly implement the electrical isolation between the first conductive pad 101 and another semiconductor device in the semiconductor structure.

[00114] In some embodiments, the material of the first dielectric layer 122 is silicon oxide and the material of the second dielectric layer 132 is silicon nitride. Thus, when silicon oxide is applied to improve the electrical insulation performance between the first conductive cushion 101 and another conductive structure in the structure Petition 870240107010, dated 12 / 16 / 2024, page 53 / 170 43 / 63 semiconductor, silicon nitride is applied to improve the hardness of the filler sublayer 102 surrounding the first conductive cushion 101, i.e., to improve the overall structural stability of the filler sublayer 102.

[00115] In some embodiments, referring to Figure 13, the first conductive cushion 101 may include a first wiring layer 131 and a second wiring layer 141. In the horizontal Y direction, a first length L1 of the first wiring layer 131 is greater than a second length L2 of the second wiring layer 141 and a first opening 112 subsequently formed that exposes a portion of the surface of the first exposed conductive cushion 101 includes: the first opening 112 that exposes a portion of the surface of the first wiring layer 131.

[00116] In some cases, the first conductive cushion 101 may be a wiring layer, and the wiring layer may be located in the peripheral region of the semiconductor structure. In one example, the wiring layer includes the first wiring layer 131 and the second wiring layer 141. Based on this, the subsequently formed first conductive cushion 101 and the first conductive interconnect structure 103 are in a one-to-one relationship.

[00117] It can be understood that the first opening subsequently formed 112 exposes the first wiring layer 131 to be subsequently connected to an electrical connection layer in another semiconductor structure, so as to implement an electrical connection between two semiconductor structures. The second wiring layer 141 located in the subfilling layer 102 can be configured to implement an electrical connection between two structures Petition 870240107010, dated 12 / 16 / 2024, page 54 / 170 44 / 63 conductors in the same semiconductor structure. Furthermore, in the horizontal Y direction, the first length L1 of the first wiring layer 131 is greater than the second length L2 of the second wiring layer 141, which subsequently facilitates the formation of a first opening 112 with a relatively large size, so as to expose the first wiring layer 131 with a larger area.

[00118] It should be noted that the first wiring layer 131 and the second wiring layer 141 in the first conductive pad 101 can be considered as the same layer structure, i.e., both are located in a film layer strip in which the first conductive pad 101 is located. However, the first wiring layer 131 and the second wiring layer 141 can be insulated from each other so as to implement an electrical connection between unused conductive structures. Furthermore, in addition to the first wiring layer 131 and the second wiring layer 141, the first conductive pad 101 may additionally include a third wiring layer, a fourth wiring layer, a fifth wiring layer, or something similar.Furthermore, the first layer of wiring 131 and the second layer of wiring 141 can be integrally formed, i.e., except for implementing different functions, the first layer of wiring 131 and the second layer of wiring 141 have the same film layer and material structure. In Figure 5, the first layer of wiring 131 and the second layer of wiring 141 are drawn in the same filling manner.

[00119] In some embodiments, still referring to Figure 13, in the horizontal Y direction, the first wiring layer 131 and the second wiring layer 141 may Petition 870240107010, dated 12 / 16 / 2024, page 55 / 170 45 / 63 additionally have an insulation layer 151 between them. For example, the first dielectric layer 122 has an insulation layer 151, which helps to improve the insulation effect between the first wiring layer 131 and the second wiring layer 141 through the insulation layer 151.

[00120] In some forms, the insulation layer 151 may be an air gap.

[00121] In some embodiments, referring to Figure 14, the first conductive cushion 101 may include a barrier layer 161 and a conductive layer 171. In the vertical X direction, the conductive layer 171 has opposite sides first and second, and the barrier layer 161 covers at least the first and second sides. It can be understood that the barrier layer 161 is configured to prevent conductive ions in the conductive layer 171 from diffusing and migrating to the subfill layer 102, so as to avoid a decrease in the conductive performance of the conductive layer 171 due to the diffusion and migration of conductive ions and to avoid a decrease in the insulating performance of the subfill layer 102 due to the migration of conductive ions, thus ensuring a relatively high conductivity of the conductive layer 171 and a relatively high insulating performance of the subfill layer 102.

[00122] It should be noted that, with reference to Figure 13 and Figure 14, both the first wiring layer 131 and the second wiring layer 141 may include a barrier layer 161 and a conductive layer 171. Hereafter in this document, the semiconductor structure shown in Figure 14 is used as an example for the description of subsequent steps. In the actual application, the first conductive pad Petition 870240107010, dated 12 / 16 / 2024, pp. 56 / 170 46 / 63 101 may alternatively include only the conductive layer 171.

[00123] In some embodiments, the barrier layer material 161 is at least one of titanium or titanium nitride and the conductive layer material 171 is aluminum. In this way, the barrier layer 161 helps to prevent the electromigration of aluminum ions.

[00124] With reference to Figure 14 and Figure 15, graphic processing is performed on the sub-coating layer 102 to form a first opening 112 and the first opening 112 exposes a portion of the surface of the first conductive pad 101.

[00125] In some embodiments, referring to Figure 14, based on the fact that the subfill layer 102 includes the first dielectric layer 122 and the second dielectric layer 132 which are stacked in the vertical X direction, after the formation of the first aperture 112, the first aperture 112 is surrounded by the remaining dielectric layer 122 and the remaining dielectric layer 132. It can be understood that in the step of performing graphic processing on the subfill layer 102, graphic processing is performed on both the first dielectric layer 122 and the second dielectric layer 132.

[00126] In some embodiments, referring to Figure 15, a portion of the surface exposed by the first conductive cushion 101 has damage 107.

[00127] In some embodiments, the damage 107 to the surface of the first conductive cushion 101 includes corrosion damage and probe contact damage. Corrosion damage may be corrosion damage caused by a corrosion process on the surface of the first conductive cushion 101 when the Petition 870240107010, dated 12 / 16 / 2024, page 57 / 170 47 / 63 Graphic processing is performed on the first dielectric layer 122 to form the first aperture 112. Probe contact damage is recorded as a mark left by physical contact between a test probe and the first conductive pad 101, performed when the first exposed conductive pad 101 is set up to test the semiconductor structure after the first aperture 112 exposes the surface of the first conductive pad 101. The probe mark damages the surface of the first conductive pad 101, for example, the surface of the first conductive pad 101 is raised. It can be understood that, regardless of recording damage or probe contact damage, the damage 107 affects the electrical contact performance between the first conductive interconnect structure 103 subsequently formed in the first aperture 112 (referring to Figure 21) and the first conductive pad 101.

[00128] It should be noted that, in Figure 15, for example, the amount of damage 107 in the first conductive cushion 101 is 2. In actual application, the amount of damage 107 in the first conductive cushion 101 is determined according to a real situation, which is not limited in any other embodiment of the present disclosure. Furthermore, the shape of the damage 107 in Figure 15 is only an example and is not limited in any embodiment of the present disclosure.

[00129] In some embodiments, still referring to Figure 15, based on the fact that the first conductive cushion 101 includes the barrier layer 161 and the conductive layer 171, in the step of performing graphic processing on the fill sublayer 102 to form the first opening 112, the first opening 112 is additionally etched to expose a barrier layer 161, that is, the first opening 112 exposes Petition 870240107010, dated 12 / 16 / 2024, pp. 58 / 170 48 / 63 the barrier layer 161, so that a first conductive interconnection structure subsequently formed 103 is directly in contact with and connected to the conductive layer 171.

[00130] In some embodiments, referring to Figure 15 to Figure 22, the filling layer 142 may additionally include a fourth dielectric layer 106. The fourth dielectric layer 106 is formed after the first opening 112 is formed and before the first conductive interconnection structure 103 is formed, so that the fourth dielectric layer 106 is located between the first conductive interconnection structure 103 and both the first dielectric layer 122 and the second dielectric layer 132.

[00131] The following describes in detail the formation step of the fourth dielectric layer 106.

[00132] With reference to Figure 15 to Figure 22, after the formation of the first opening 112, and before the formation of the first conductive interconnection structure 103, the manufacturing method may additionally include the following steps: The fourth dielectric layer 106 is formed and at least a portion of the damage 107 in the first conductive cushion 101 is removed, wherein the fourth dielectric layer 106 is located on the side wall of the first opening 112.

[00133] It should be noted that, in Figure 18, for example, the damage 107 on the first conductive pad 101 is removed. In actual application, due to a limitation in the recording process or other requirement, a small amount of the damage 107 on the first conductive pad 101 may be retained.

[00134] Forming the fourth dielectric layer 106 and removing at least a portion of the damage 107 in the first conductive cushion 101 includes at least the following two embodiments. Petition 870240107010, dated 12 / 16 / 2024, page 59 / 170 49 / 63

[00135] In some embodiments, referring to Figure 16, a first opening 112 exposes a portion of the upper surface of a first conductive cushion 101, the thickness of the first conductive cushion 101 whose upper surface is exposed by the first opening 112 is a first thickness D1, the thickness of a first conductive cushion 101 whose upper surface is not exposed by the first opening 112 is a second thickness D2, and the first thickness D1 is less than the second thickness D2.

[00136] It can be understood that the first conductive pad 101 whose upper surface is exposed by the first opening 112 is a second portion 121 and the first thickness D1 is the thickness of the second portion 121; and the first conductive pad 101 whose upper surface is not exposed by the first opening 112 is a first portion 111 and the second thickness D2 is the thickness of the first portion 111. Since the second portion 121 of a partial thickness is also recorded in the formation step of the first opening 112, the first thickness D1 is less than the second thickness D2, so that the upper surface 100a of the first substrate 100 is used as a reference and the upper surface 121a of the second portion 121 is lower than the upper surface 111a of the first portion 111.

[00137] In some other embodiments, for example, the semiconductor structure shown in Figure 5 is formed, and the same first aperture 112 exposes upper surfaces of multiple first conductive pads 101. In this way, orthographic projections of at least two first conductive pads 101 onto the first substrate 100 overlap with an orthographic projection of a first structure of Petition 870240107010, dated 12 / 16 / 2024, pages 60 / 170 50 / 63 conductive interconnection 103 subsequently formed in a first opening 112 in the first substrate 100, so that the first conductive cushion 101 and the first conductive interconnection structure 103 are in a multiple-to-one relationship.

[00138] In some embodiments, the steps of forming the fourth dielectric layer 106 and removing at least a portion of the damage 107 in the first conductive cushion 101 may include: formation of an initial fourth dielectric layer 116 with reference to Figure 16 and Figure 17, wherein the initial fourth dielectric layer 116 conformally covers the surface of the first opening 112 and the upper surface 102a of the underfill layer 102. It may be understood that the initial fourth dielectric layer 116 may cover the damage 107 and the upper surface 102a of the underfill layer 102 is the upper surface 132a of the second dielectric layer 132 (referring to Figure 2).

[00139] It should be noted that when the first conductive cushion 101 includes the first wiring layer 131 and the second wiring layer 141, the exposed wiring layer is the first wiring layer 131.

[00140] With reference to Figure 17 and Figure 18, the initial fourth dielectric layer 116 is recessed by etching to remove the initial fourth dielectric layer 116 located on the upper surface 102a of the filler sublayer 102 and on the lower part of the first opening 112, and the remaining initial fourth dielectric layer 116 is the fourth dielectric layer. 106. In the corrosion stage of the initial fourth dielectric layer 116, a partial thickness of the first conductive cushion 101 exposed by the first opening 112 is further corroded. Petition 870240107010, dated 12 / 16 / 2024, pp. 61 / 170 51 / 63 in the vertical X direction. In other words, a partial thickness of the first conductive cushion 101 exposed by the first opening 112 is corroded.

[00141] It can be understood that in the corrosion step of the initial fourth dielectric layer 116 to form the fourth dielectric layer 106, when the corrosion process removes the initial fourth dielectric layer 116 located at the bottom of the first opening 112, the damage 107 covered by the initial fourth dielectric layer 116 is also removed, i.e., the second portion 121 is corroded, so as to remove at least a portion of the damage 107 and at the same time, the fourth dielectric layer 106 located on the side wall of the first opening 112 is configured to prevent corrosion of the filling sublayer 102 that constitutes the side wall of the first opening 112. Furthermore, the steps of forming the fourth dielectric layer 106 and removing at least a portion of the damage 107 can be performed synchronously.Thus, in the damage etching step 107, the fourth dielectric layer 106 is configured to protect the side wall of the first opening 112, so as to prevent etching of the first dielectric layer 122 that constitutes the side wall of the first opening 112, so that the side wall of the first opening 112 has a relatively flat interface and, subsequently, a first conductive interconnection structure 103 with a flat size is formed. Furthermore, in the damage etching step 107, a possible pollutant on the surface of the first conductive cushion 101 can be additionally removed through an etching process, which helps to further reduce contact resistance between the first conductive interconnection structure 103 subsequently formed and the... Petition 870240107010, dated 12 / 16 / 2024, pp. 62 / 170 52 / 63 first driver cushion 101.

[00142] In actual application, the thickness of the second engraved portion 121 is adjusted according to the setting of a parameter of the engraving process, in order to ensure that the damage 107 is completely removed.

[00143] In some embodiments, still referring to Figure 18, in the etching step of the initial fourth dielectric layer 116 to form the fourth dielectric layer 106 based on the conductive layer 171 exposed by the first opening 112, the etching process may additionally etch a partial thickness of the conductive layer 171, i.e., etch a partial thickness of the second portion 121, in the vertical direction X. In the actual application, the first opening may expose a barrier layer. In the etching step of the initial fourth dielectric layer to form the fourth dielectric layer, the etching process removes at least one barrier layer exposed by the first opening, so that a first conductive interconnection structure subsequently formed is in direct contact and connected to the conductive layer.

[00144] It should be noted that in Figure 16 to Figure 18, a first portion 111 and a second portion 121 are divided with a thick dashed line and the division of the first portion 111 and the second portion 121 in the first conductive cushion 101 depends on the area of ​​the first conductive cushion 101 exposed by the first opening 112.

[00145] In some other embodiments, referring to Figure 16, a first conductive cushion 101 whose upper surface is exposed by the first opening 112 is the second portion 121, a first conductive cushion 101 whose upper surface is not exposed by the first opening 112 is the first Petition 870240107010, dated 12 / 16 / 2024, pp. 63 / 170 53 / 63 portion 111 and the exposed surface of the second portion 121 has damage 107. The steps for forming the fourth dielectric layer 106 and removing at least a portion of the damage 107 in the first conductive cushion 101 may include: forming a masking layer 108 with reference to Figure 16 and Figure 19, wherein the masking layer 108 is located on the side wall of the first opening 112 and on the upper surface 102a of the filling sublayer 102 and the masking layer 108 exposes a portion of the upper surface of the first conductive cushion 101 exposed by the first remaining opening 112, i.e., a portion of the upper surface of the second portion 121.

[00146] With reference to Figure 19 and Figure 20, damage 107 is recorded with mask layer 108 as a mask to record a partial thickness of the first conductive pad 101 exposed by the first opening 112 in the vertical X direction. In this way, it is advantageous to protect the fill sublayer 102 by mask layer 108 in the step of recording damage 107.

[00147] With reference to Figure 20 and Figure 18, mask layer 108 is removed and the fourth dielectric layer 106 is formed.

[00148] It should be noted that the manufacturing method provided in another embodiment of the present disclosure does not establish any limitations for a method of forming the fourth dielectric layer 106 after the mask layer 108 is removed. In some embodiments, the step of forming the fourth dielectric layer 106 may include: first forming a protective film that conformably covers the first opening after the mask layer is removed and the second upper surface of the first dielectric layer, and then etching the protective film. Petition 870240107010, dated 12 / 16 / 2024, pp. 64 / 170 54 / 63 to form the fourth dielectric layer 106.

[00149] It can be understood that, after the removal of the damage 107, the fourth dielectric layer 106 is formed, so as to prevent a protective film used for the next fourth dielectric layer 106 from being exposed to a corrosive environment for too long, which thus improves the uniformity of the film layer of the fourth dielectric layer 106 formed and improves the blocking effect of the fourth dielectric layer 106 on the diffusion and migration of conductive ions in the first conductive interconnection structure 103 subsequently formed.

[00150] S103: A first conductive interconnect structure 103 that fills the first opening 112 is formed. In some embodiments, with reference to Figure 15 and Figure 21, the fourth dielectric layer is not formed on the side wall of the sub-filling layer 102 and the first conductive interconnect structure 103 is formed directly in the first opening 112. In actual application, if the first conductive cushion 101 has damage 107, the first conductive interconnect structure 103 covers the damage 107.

[00151] In some other embodiments, with reference to Figure 18 and Figure 22, the step of filling the first opening 112 with the first conductive interconnection structure 103 based on the formation of the fourth dielectric layer 106, i.e., removing the damage 107 (referring to Figure 16) includes: filling the remaining portion of the first opening 112 with the first conductive interconnection structure 103. It can be understood that the fourth dielectric layer 106 and the first conductive interconnection structure 103 jointly fill the first opening 112.

[00152] It should be noted that the formation of Petition 870240107010, dated 12 / 16 / 2024, pages 65 / 170 55 / 63 The first conductive interconnection structure 103 and the second conductive cushion 105 are subsequently described in detail by means of the semiconductor structure shown in Figure 18.

[00153] In some embodiments, with reference to Figure 18 and Figure 23, the step of forming the first conductive interconnection structure 103 may include: forming a first diffusion barrier layer 113, wherein the first diffusion barrier layer 113 conformably covers the inner wall of the first opening 112 and the upper surface 102a of the filling sublayer 102; forming a first seed layer 123, wherein the first seed layer 123 conformally covers the surface of the first diffusion barrier layer 113; and forming a first galvanizing layer 133, wherein the first galvanizing layer 133 fills the remaining portion of the first opening 112 and is located on the upper surface 123a of the first seed layer 123, distant from the filling sublayer 102.

[00154] With reference to Figure 23 and Figure 24, the leveling process is carried out on the first diffusion barrier layer 113, the first seed layer 123 and the first coating layer 133 until the upper surface 102a of the underfill layer 102 is exposed and the remaining layer of the first diffusion barrier 113, the remaining layer of the first seed 123 and the remaining layer of the first coating 133 constitute the first conductive interconnection structure 103.

[00155] It can be understood that the first coating layer 133 is formed based on the first seed layer 123 through a coating process, which helps to improve the conductivity of the first coating layer. Petition 870240107010, dated 12 / 16 / 2024, pp. 66 / 170 56 / 63 133, in order to further improve the overall conductivity of the first conductive interconnection structure 103. Furthermore, the first diffusion barrier layer 113 is configured to prevent conductive ions in the first seed layer 123 and the first coating layer 133 from diffusing and migrating to the subfill layer 102, so as to avoid a decrease in the conductive performance of the first seed layer 123 and the first coating layer 133 due to the diffusion and migration of conductive ions, and a decrease in the insulation performance of the subfill layer 102 due to the migration of conductive ions. That is, it is ensured that the conductive performance of the first seed layer 123 and the first coating layer 133 is relatively high, and the insulation performance of the subfill layer 102 is relatively high.

[00156] In some embodiments, the material of the first diffusion barrier layer 113 is at least one of tantalum or tantalum nitride and the material of the first seed layer 123 and the first electroplating layer 133 is copper. In this way, the first diffusion barrier layer 113 helps to prevent the electromigration of copper ions.

[00157] In some embodiments, after the first conductive interconnect structure 103 is formed in the first opening 112, leveling processing is performed on the surface of the first conductive interconnect structure 103, so that a first predetermined height difference H1 exists between the upper surface 132a of the second dielectric layer 132 and the upper surface 103a of the first conductive interconnect structure 103 with reference to Figure 2, wherein the range of the first height difference Petition 870240107010, dated 12 / 16 / 2024, pp. 67 / 170 57 / 63 predetermined H1 is from 0 nm to 50 nm.

[00158] In some embodiments, referring to Figure 24 to Figure 27, S104: multiple second conductive cushions 105 are formed on the first conductive interconnection structure 103, such that at least one of the first conductive cushions 101 and at least one of the second conductive cushions 105 are electrically connected through the first conductive interconnection structure 103.

[00159] In some embodiments, referring to Figure 24 to Figure 27, after the formation of the first conductive interconnection structure 103, the dielectric layer 104 is formed and the second conductive cushion 105 electrically connected to the first conductive interconnection structure 103 is formed in the dielectric layer 104.

[00160] In some embodiments, referring to Figure 27, the step of forming the second conductive cushion 105 may include: forming at least two second conductive cushions 105 in contact with and connected to the upper surface 103a of the first conductive interconnect structure 103 distant from the first conductive cushion 101. It can be understood that a first conductive interconnect structure 103 is in contact with and connected to at least two second conductive cushions 105, which helps to improve the transmission efficiency of an electrical signal between the first conductive cushion 101, the first conductive interconnect structure 103 and the second conductive cushion 105.

[00161] It should be noted that, in Figure 27, for example, a first conductive interconnect structure 103 is connected to three second conductive pads 105. In the actual application, a quantity of second conductive pads 105 in Petition 870240107010, dated 12 / 16 / 2024, pp. 68 / 170 58 / 63 contact with and connected to the same first conductive interconnection structure 103 can be determined according to an actual requirement, for example, the quantity can be one, two, four or five.

[00162] In some embodiments, forming at least two second conductive cushions 105 may include the following steps:

[00163] With reference to Figure 25, a dielectric layer 104 is formed on the upper surface formed jointly by the sub-filler layer 102 and the first conductive interconnection structure 103.

[00164] In some embodiments, still referring to Figure 25, the third dielectric layer 124 and the first bonding layer 134 are stacked on the second dielectric layer 132 and the third dielectric layer 124 and the first bonding layer 134 constitute the dielectric layer 104. It can be understood that the third dielectric layer 124 and the first bonding layer 134 jointly implement the electrical insulation between the second conductive cushion 105 subsequently formed in the dielectric layer 104 and another conductive structure in the semiconductor structure.

[00165] In some embodiments, the material of the third dielectric layer 124 is silicon oxide and the material of the first bonding layer 134 is silicon nitride. Thus, when silicon oxide is used to improve the electrical insulation performance between the second conductive cushion 105 subsequently formed in the third dielectric layer 124 and another conductive structure in the semiconductor structure, silicon nitride is used to improve the hardness of the dielectric layer 104, i.e., to improve the Petition 870240107010, dated 12 / 16 / 2024, pp. 69 / 170 59 / 63 mechanical stability of the entire structure.

[00166] With reference to Figure 25 and Figure 26, graphic processing is performed on the dielectric layer 104 to form multiple secondary openings 114 spaced apart from each other. At least two secondary openings 114 expose different regions of the upper surface 103a of the same first conductive interconnection structure 103 and other secondary openings 114 expose the upper surface 102a of the subfiller layer 102 of the filler layer 142.

[00167] It can be understood that a first conductive interconnect structure 103 in contact with and connected to the second conductive cushion 105 is formed in the subfilling layer 102. Only the second opening 114 needs to be formed in the dielectric layer 104, and the second conductive cushion 105 filling the second opening 114 is subsequently formed. Thus, the depth of the second opening 114 used to form the second conductive cushion 105 is related only to the thickness of the dielectric layer 104. Even though the width of the second opening 114 in the horizontal Y direction is less than the width of the first conductive interconnect structure 103 in the horizontal Y direction, the ratio between the depth and width of the second opening 114 is not very large. It is not easy to leave a recording byproduct at the contact between the first conductive interconnect structure 103 and the second conductive cushion 105.The byproduct of the recording in this document comes primarily from the step of performing graphic processing on the 104 dielectric layer.

[00168] With reference to Figure 26 and Figure 27, a second diffusion barrier layer 115 is formed and the second diffusion barrier layer 115 covers accordingly Petition 870240107010, dated 12 / 16 / 2024, pp. 70 / 170 60 / 63 the inner wall of the second opening 114. A second seed layer 125 is formed, wherein the second seed layer 125 conformably covers the surface of the second diffusion barrier layer 115. A second coating layer 135 is formed, the second coating layer 135 fills the remaining portion of the second opening 114 and the second diffusion barrier layer 115, the second seed layer 125 and the second coating layer 135 form the second conductive cushion 105.

[00169] It can be understood that the second coating layer 135 is formed based on the second seed layer 125 through a coating process, which helps to improve the conductivity of the second coating layer 135, so as to additionally improve the overall conductivity of the second conductive cushion 105. Furthermore, the second diffusion barrier layer 115 is configured to prevent conductive ions in the second seed layer 125 and the second coating layer 135 from diffusing and migrating to the dielectric layer 104, so as to avoid a decrease in the conductive performance of the second seed layer 125 and the second coating layer 135 due to the diffusion and migration of conductive ions and a decrease in the insulation performance of the dielectric layer 104 due to the migration of conductive ions.In other words, it is guaranteed that the conductivity of the second seed layer 125 and the second coating layer 135 is relatively high, and the insulation performance of the dielectric layer 104 is relatively high.

[00170] In some embodiments, the material of the second diffusion barrier layer 115 is at least one of tantalum or tantalum nitride and the material of the second Petition 870240107010, dated 12 / 16 / 2024, pp. 71 / 170 The 61 / 63 seed layer 125 and the second galvanizing layer 135 are copper. Therefore, the second diffusion barrier layer 115 helps prevent the electromigration of copper ions.

[00171] It should be noted that in Figure 27, the first diffusion barrier layer 113 and the second diffusion barrier layer 115 are drawn in the same filling manner. In actual application, the materials of the first diffusion barrier layer 113 and the second diffusion barrier layer 115 may be the same or different.

[00172] In some embodiments, referring to Figure 8, the filler layer may additionally include a first bonding layer 134, the second conductive pad 105 has an exposed upper surface on the first bonding layer 134, a second predetermined height difference H2 exists between the upper surface of the second conductive pad 105 exposed on the first bonding layer 134 and the upper surface of the first bonding layer 134, and the range of the second predetermined height difference H2 is from 0 nm to 50 nm. After the second conductive pad 105 is formed, the fabrication method may additionally include: forming a second bonding layer 234 directly bonded to the first bonding layer 134 and a third conductive pad 205 directly bonded to the second conductive pad 105.

[00173] It should be noted that the formation step of the third conductive cushion 205 is similar to the formation step of the second conductive cushion 105 and the details are not described again in this document.

[00174] In conclusion, after the formation of the first opening 112 which exposes the first conductive cushion 101, the first conductive interconnection structure 103 is formed in Petition 870240107010, dated 12 / 16 / 2024, pp. 72 / 170 62 / 63 first opening 112, so as to omit the step of forming an insulating layer that fills the first opening 112 and forms a through to form a conductive pillar in the insulating layer, thus simplifying a step in the process of preparing a semiconductor structure. Furthermore, the first conductive interconnect structure 103 is formed in the first opening 112. On the one hand, this helps to increase the contact area between the first conductive interconnect structure 103 and the first conductive cushion 101, so as to reduce the contact resistance between the first conductive interconnect structure 103 and the first conductive cushion 101.On the other hand, the first conductive interconnect structure 103 in contact with and connected to the first conductive cushion 101 does not need to be formed in such a way as to engrave a deep hole, i.e., to avoid the generation of a hard-to-remove engraving byproduct, so as to avoid the existence of an engraving byproduct between the first conductive cushion 101 and the first conductive interconnect structure 103 or in the first conductive interconnect structure 103, thus helping to improve the conductivity of the first conductive interconnect structure 103, reducing contact resistance between the first conductive interconnect structure 103 and the first conductive cushion 101 and avoiding poor contact between the first conductive interconnect structure 103 and the first conductive cushion 101, so as to improve the electrical performance of the semiconductor structure.

[00175] A person with average skill in the art can understand that the previous implementations are specific modalities for implementing the present disclosure. In a real application, various modifications can be made to the forms Petition 870240107010, dated 12 / 16 / 2024, pp. 73 / 170 63 / 63 and details of the implementations without departing from the spirit and scope of the embodiments of this disclosure. Anyone skilled in the art may make alterations and modifications without departing from the spirit and scope of the embodiments of this disclosure. Therefore, the scope of protection of the embodiments of this disclosure will be subject to the scope defined by the claims. Petition 870240107010, dated 12 / 16 / 2024, pp. 74 / 170

Claims

1 / 6 CLAIMS 1. SEMICONDUCTOR STRUCTURE characterized by comprising: a first substrate and a semiconductor device located on the first substrate; a plurality of first conductive pads, connected to the semiconductor device; a plurality of second conductive pads, at least one of the first conductive pads and at least one of the second conductive pads being electrically connected through a first conductive interconnection structure extending in a direction perpendicular to the first substrate; and a fill layer, wherein the fill layer is filled on an outer periphery of each of the first conductive pads, the first conductive interconnection structure and each of the second conductive pads, wherein the first conductive interconnection structure has a surface buried by the fill layer between adjacent conductive pads.

2. SEMICONDUCTOR STRUCTURE, according to claim 1, characterized in that the filling layer comprises a first dielectric layer, a second dielectric layer and a third dielectric layer, the first dielectric layer covering the first conductive pad, the third dielectric layer covering a side wall of the second conductive pad, the second dielectric layer being located between the first dielectric layer and the third dielectric layer, there is a first predetermined height difference between an upper surface of the second dielectric layer and an upper surface of the first conductive interconnect structure and a range of the first predetermined height difference is from 0 nm to 50 nm.

3. SEMICONDUCTOR STRUCTURE, according to claim 2, characterized in that the first dielectric layer and the second dielectric layer constitute a filling sublayer; and the filling layer further comprises a fourth dielectric layer, and the fourth dielectric layer is located between the filling sublayer and the first conductive interconnection structure.

4. SEMICONDUCTOR STRUCTURE, according to claim 2, characterized in that at least one of the second conductive pads is located on the upper surface of the second dielectric layer.

5. SEMICONDUCTOR STRUCTURE, according to claim 4, characterized in that the second conductive pad located on the upper surface of the second dielectric layer is not electrically connected to the first conductive pad and the second conductive pad is in direct contact with the upper surface of the second dielectric layer.

6. SEMICONDUCTOR STRUCTURE, according to claim 1, characterized in that at least one of the first conductive pads in electrical contact with the first conductive interconnection structure comprises a first portion and a second portion, the second portion being in direct contact with the first conductive interconnection structure, the first portion not being in direct contact with the first conductive interconnection structure, and a surface of the second portion in direct contact with the first conductive interconnection structure having a smaller portion than a surface of the first portion.

7. SEMICONDUCTOR STRUCTURE, according to claim 1, characterized in that orthographic projections of at least two of the first conductive pads on the first substrate overlap with an orthographic projection of a first conductive interconnection structure on the first substrate.

8. SEMICONDUCTOR STRUCTURE, according to claim 1, characterized in that the filling layer comprises a first bonding layer, wherein at least one of the second conductive pads has an upper surface exposed in the first bonding layer, there is a second predetermined height difference between the upper surface of at least one of the second conductive pads exposed in the first bonding layer and an upper surface of the first bonding layer, and the range of the second predetermined height difference is from 0 nm to 50 nm.

9. SEMICONDUCTOR STRUCTURE, according to claim 8, characterized by further comprising a second bonding layer and a plurality of third conductive pads located in the second bonding layer, wherein the second bonding layer is directly bonded to the first bonding layer and the third conductive pads are directly bonded to the second conductive pads.

10. SEMICONDUCTOR STRUCTURE, according to claim 1, characterized by further comprising an insulating layer, wherein the insulating layer is located in the filler layer between the first adjacent conductive pads.

11. MANUFACTURING METHOD FOR A SEMICONDUCTOR STRUCTURE Petition 870260068418, dated 10 / 07 / 2026, page 7 / 15 4 / 6 characterized by comprising: providing a first substrate, wherein the first substrate has a semiconductor device; forming a plurality of first conductive pads connected to the semiconductor device; forming a first opening, wherein the first opening exposes a surface of at least one of the first conductive pads; forming a first conductive interconnect structure that fills the first opening; and forming a plurality of second conductive pads on the first conductive interconnect structure, such that at least one of the first conductive pads and at least one of the second conductive pads are electrically connected through the first conductive interconnect structure;wherein a fill layer is formed on the outer periphery of each of the first conductive pads, each of the second conductive pads, and the first conductive interconnection structure has a surface buried by a fill layer between adjacent conductive pads.

12. MANUFACTURING METHOD, according to claim 11, characterized by the filling layer comprising a first dielectric layer, a second dielectric layer and a third dielectric layer, the first conductive pads being formed in the first dielectric layer, the second dielectric layer being formed above the first dielectric layer, the first dielectric layer and the second dielectric layer being formed before the first Petition 870260068418, dated 10 / 07 / 2026, p.8 / 15 5 / 6 an opening is formed and the first opening is formed in the first dielectric layer and in the second dielectric layer; after the first conductive interconnection structure is formed in the first opening, leveling processing is performed on a surface of the first conductive interconnection structure, so that there is a first predetermined height difference between an upper surface of the second dielectric layer and an upper surface of the first conductive interconnection structure, in which a range of the first predetermined height difference is from 0 nm to 50 nm; and after the formation of the first conductive interconnection structure, the third dielectric layer is formed and the second electrically connected conductive cushions to the first conductive interconnection structure are formed in the third dielectric layer.

13. MANUFACTURING METHOD, according to claim 12, characterized in that the filling layer further comprises a fourth dielectric layer, the fourth dielectric layer being formed after the first opening is formed and before the first conductive interconnection structure is formed, such that the fourth dielectric layer is located between the first conductive interconnection structure and both the first dielectric layer and the second dielectric layer.

14. MANUFACTURING METHOD, according to claim 13, characterized by the fourth dielectric layer formation step comprising: forming an initial fourth dielectric layer, wherein the initial fourth dielectric layer conformably covers a surface of the first opening and the upper surface of the second dielectric layer; and corroding the initial fourth dielectric layer to remove the initial fourth dielectric layer located on the upper surface of the second dielectric layer and a surface of the lower part of the first opening, the remaining initial fourth dielectric layer being the fourth dielectric layer, wherein in the initial fourth dielectric layer corrosion step, a partial thickness of the first conductive cushion exposed by the first opening is corroded.

15. MANUFACTURING METHOD, according to claim 11, characterized in that the filler layer further comprises a first bonding layer, at least one of the second conductive pads having an exposed upper surface in the first bonding layer, a second predetermined height difference exists between the upper surface of at least one of the second conductive pads exposed in the first bonding layer and an upper surface of the first bonding layer, and the range of the second predetermined height difference is from 0 nm to 50 nm; and after the formation of the second conductive pads, the method further comprises: forming a second bonding layer directly bonded to the first bonding layer and a third conductive pad directly bonded to the second conductive pads. Petition 870260068418, dated 10 / 07 / 2026, page 10 / 15

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