Scanning driver and display device including the same

Description

1 / 44 Scanning driver and display device including the same FIELD OF TECHNIQUE

[0001] The present invention relates to a scanning driver and a display device including the same. BACKGROUND OF THE INVENTION

[0002] As the information society develops, the demands for display devices to show images are increasing in various ways. For example, display devices are applied to various electronic devices such as smartphones, digital cameras, notebook computers, navigation devices, and smart televisions.

[0003] Display devices can be flat panel display devices such as liquid crystal display devices, quantum dot display devices, and organic light-emitting display devices.

[0004] A display device includes a display panel that includes data lines, scan signal lines and a plurality of pixels connected to the data lines and scan signal lines, a scan driver that provides scan signals to the scan signal lines and a data driver that provides data voltages to the data lines.

[0005] The sweep driver can be formed in an area without display of the display panel. The sweep driver formed in the display panel includes a plurality of thin-film transistors that are switched on and off in response to gate control signals. Since the thin-film transistors of the sweep driver are kept on or off for a certain period of time, the operating characteristics, such as operating conditions, of the thin-film transistors must be kept constant. Petition 870250088599, dated 09 / 30 / 2025, page 43 / 96 2 / 44 SUMMARY OF THE INVENTION ASPECTS TO BE ACHIEVED BY THE INVENTION

[0006] Aspects of the present invention provide a sweep driver capable of enhancing the material of a semiconductor layer to reduce the electrical stress of thin-film transistors to which it is subjected due to the amount of current or self-rising voltage and a display device that includes the sweep driver.

[0007] Aspects of the present invention also provide a sweep driver capable of raising or adjusting electrical characteristics to enhance the material of a semiconductor layer of at least one thin-film transistor directly connected to a load node of each sweep signal output stage, and a display device including the sweep driver.

[0008] However, aspects of the present invention are not limited to those set forth in this document. The above aspects and other aspects of the present invention will become more apparent to a person skilled in the art to whom the present invention pertains by referring to the detailed description of the present invention given below. MEANS OF ACHIEVING THE ASPECTS OF THE INVENTION

[0009] According to one embodiment of the invention, a sweep driver comprising stages that sequentially emit sweep signals to sweep signal lines during an active period of an Nth frame, wherein N is a positive integer, and at least one of the stages comprises an output node controller that provides a gate activation voltage to a load node in response to a gate control signal from a display driver; and an output controller that emits a sweep clock signal, which is fed into a sweep clock terminal, to a line of Petition 870250088599, dated 09 / 30 / 2025, page 44 / 96 3 / 44 scan signal connected as a scan signal when gate activation voltage is supplied to the load node.

[00010] In one embodiment, the output node controller comprises at least one thin-film transistor that includes a first active layer, and is directly or indirectly connected to the load node, and at least one other thin-film transistor that includes a second active layer in which a different oxide semiconductor material is used than the oxide semiconductor material of the first active layer, and is directly connected to the load node.

[00011] According to one embodiment of the invention, a display device comprising a plurality of pixels arranged in a display area of ​​a display panel, a touch detection unit mounted on the front of the display panel and integrally formed with the display panel, a touch driver that detects a touch using a plurality of touch electrodes arranged in the touch detection unit, a display driver that controls data voltages supplied to the pixels and image display timing of the pixels, and a scan driver that sequentially drives scan signal lines, which are connected to the pixels, in response to a gate control signal from the display driver.

[00012] In one embodiment, the sweep driver comprises stages that sequentially emit sweep signals to sweep signal lines during an active period of an Nth frame, wherein N is a positive integer, and at least one of the stages comprises an output node controller that provides a gate activation voltage to a load node in response to a gate control signal from a display driver; and an output controller that emits a sweep clock signal, which is fed into a sweep clock terminal, to a connected sweep signal line as a sweep signal when the gate activation voltage is Petition 870250088599, dated 09 / 30 / 2025, page 45 / 96 4 / 44 supplied for the load node.

[00013] In one embodiment, the output node controller comprises at least one thin-film transistor comprising an active first layer and is indirectly connected to the load node, and at least one other thin-film transistor comprising an active second layer comprising a semiconductor oxide material different from the active first layer, and is indirectly connected to the load node. EFFECTS OF THE INVENTION

[00014] A sweep driver and a display device that includes the same according to the embodiments can reduce the electrical stress of thin-film transistors and enhance reliability by enhancing the material of a semiconductor layer of a thin-film transistor that is subjected to stress due to the amount of current or self-voltage rise, etc.

[00015] Furthermore, a sweep driver and a display device that includes the same according to the embodiments may enhance or stabilize electrical characteristics such as high-speed drive, operating range variation, and limit voltage fluctuation suppression by enhancing the material of a semiconductor layer of at least one thin-film transistor directly connected to a load node of each sweep signal output stage.

[00016] However, the effects of the present invention are not limited to those set forth in this document. The above effects and other effects of the present invention will become more apparent to a person skilled in the art to which the present invention pertains by reference to the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[00017] Figure 1 is a perspective view of a display device according to an embodiment; Petition 870250088599, dated 09 / 30 / 2025, page 46 / 96 5 / 44

[00018] Figure 2 is a cross-sectional view of the display device according to the embodiment;

[00019] Figure 3 is a plan view of a display unit of the display device according to the embodiment;

[00020] Figure 4 is a block diagram of a display panel and a display driver according to an embodiment;

[00021] Figure 5 is an example diagram of a scanning driver according to an embodiment of the present invention;

[00022] Figure 6 is a detailed circuit diagram of a first embodiment of an nth stage of the sweep driver illustrated in Figure 5;

[00023] Figure 7 is a waveform diagram illustrating changes in voltage levels of detection control signals, sweep clock signals, and a load node during an active period of an Nth-frame period;

[00024] Figure 8 is a detailed circuit diagram of a second embodiment of the nth stage of the sweep driver illustrated in Figure 5;

[00025] Figure 9 is a cross-sectional view illustrating the cross-sectional structure of the first and sixth transistors of the sweep driver illustrated in Figure 8;

[00026] Figure 10 is a diagram of another embodiment of an nth stage of the scan driver illustrated in Figure 8;

[00027] Figure 11 is a cross-sectional view illustrating the cross-sectional structure of the fourth and sixth transistors of the sweep driver illustrated in Figure 10;

[00028] Figures 12 and 13 are perspective views of an example application of a display device according to an embodiment of the present invention; and

[00029] Figures 14 and 15 are perspective views of an example. Petition 870250088599, dated 09 / 30 / 2025, page 47 / 96 6 / 44 application of a display device according to another embodiment of the present invention. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[00030] The present invention will now be described more fully in this document with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should be interpreted as limited to the embodiments set forth in this document. Instead, these embodiments are provided so that this invention is thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[00031] It will also be understood that when a layer is referred to as being on another layer or substrate, this may be directly on the other layer or substrate or intervening layers may also be present. The same numerical references indicate the same components throughout the descriptive report.

[00032] It will be understood that, although the terms “first,” “second,” etc. may be used in this document to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another element. For example, a first element discussed below could be called a second element without departing from the teachings of the present invention. Similarly, the second element could also be called the first element.

[00033] Each of the features of the various embodiments of the present invention can be combined or combined with each other, in part or in whole, and technically various interlocks and actuations are possible. Each embodiment can be implemented independently of the others or can be implemented together in an association. Petition 870250088599, dated 09 / 30 / 2025, page 48 / 96 7 / 44

[00034] Hereafter, specific embodiments will be described with reference to the attached drawings.

[00035] Figure 1 is a perspective view of a display device according to an embodiment.

[00036] With reference to Figure 1, a display device 10 can be applied to portable electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), mobile communication terminals, electronic notebook computers, e-books, portable multimedia layers (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 can be applied as a display unit for a television, a notebook computer, a monitor, a sign, or an Internet of Things (IoT) device. As another example, the display device 10 can be applied to wearable devices such as smartwatches, watch phones, eyeglasses, and head-mounted displays (HMDs).

[00037] The display device 10 may have a flat shape similar to a square. For example, the display device 10 may have a flat shape similar to a square that has short sides in a first direction DR1 and long sides in a second direction DR2. Each corner where a short side extending in the first direction DR1 meets a long side extending in the second direction DR2 may be rounded with a predetermined curvature or may have a right angle. The flat shape of the display device 10 is not limited to a square shape, but may also be similar to other polygonal shapes, a circular shape, or an elliptical shape.

[00038] The display device 10 may include a display panel 100, a display driver 200, a circuit board 300, a touch driver 400 and a power supply unit 500.

[00039] Display panel 100 may include a main area MA Petition 870250088599, dated 09 / 30 / 2025, page 49 / 96 8 / 44 and an SBA subarea.

[00040] The main area MA may include a display area DA that includes pixels displaying an image and a non-display area NDA arranged around the display area DA. The display area DA may emit light from a plurality of emission areas or a plurality of aperture areas. For example, display panel 100 may include pixel circuits that include switching elements, a pixel definition layer that defines the emission areas or the aperture areas, and self-emitting light elements.

[00041] For example, each of the self-emitting light elements may include, but is not limited to, at least one of an organic light-emitting diode including an organic light-emitting layer, a quantum dot light-emitting diode including a quantum dot light-emitting layer, an inorganic light-emitting diode including an inorganic semiconductor, and a miniature light-emitting diode.

[00042] The non-display NDA area may be an area outside the display DA area. The non-display NDA area may be defined as an area outside the main MA area of ​​display panel 100. The non-display NDA area may include a gate driver (not shown) that provides the gate signals to the gate lines and fan-out lines (not shown) that connect the display driver 200 and the display DA area.

[00043] The SBA subarea may extend from one side of the main MA area. The SBA subarea may include a flexible material that can be flexed, bent, rolled, etc. For example, when the SBA subarea is flexed, it may overlap the main MA area in a thickness direction (e.g., a third direction DR3). The SBA subarea may include the display driver 200 and the filling units connected to the circuit board 300. Optionally, the SBA subarea may be omitted, and the display driver 200 and the units of Petition 870250088599, dated 09 / 30 / 2025, page 50 / 96 9 / 44 filler can be placed in the non-display area. NDA.

[00044] The display driver 200 can output signals and voltages to drive the display panel 100. The display driver 200 can provide data voltages for DL ​​data lines. The display driver 200 can provide a power supply voltage for a power line and provides a gate control signal for a scan driver (or gate driver). The display driver 200 can be formed as an integrated circuit (IC) and mounted on the display panel 100 by a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 can be arranged in the SBA subarea and can be overlaid by the main MA area in the thickness direction (third direction DR3) by bending the SBA subarea. For another example, the display driver 200 can be mounted on the circuit board 300.

[00045] The circuit board 300 can be fixed to the display panel filler units 100 using an anisotropic conductive layer. The conductive lines of the circuit board 300 can be electrically connected to the display panel filler units 100. The circuit board 300 can be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip-on-film.

[00046] The touch driver 400 can be mounted on the circuit board 300. The touch driver 400 can be electrically connected to a touch detection unit of the display panel 100. The touch driver 400 can provide a touch drive signal to a plurality of touch electrodes of the touch detection unit and detect a change in capacitance between the touch electrodes. For example, the touch drive signal can be a pulse signal that has a predetermined frequency. The touch driver 400 can determine if an input has been made and calculate the input coordinates. Petition 870250088599, dated 09 / 30 / 2025, page 51 / 96 10 / 44 based on a change in capacitance between the touch electrodes. The 400 touch driver can be formed as an integrated circuit (IC).

[00047] The power supply unit 500 can be arranged on the circuit board 300 to provide a power supply voltage for the display driver 200 and the display panel 100. The power supply unit 500 can generate a first drive voltage and supply the first drive voltage to the first drive voltage lines VDL, it can generate a startup voltage and supply the startup voltage to the startup voltage lines VIL, and it can generate a common voltage and supply the common voltage to a common electrode, common to the light-emitting elements of a plurality of pixels. For example, the first drive voltage can be a high-potential voltage to drive the light-emitting elements, and each of the common voltage and the second drive voltage can be a low-potential voltage to drive the light-emitting elements.

[00048] Figure 2 is a cross-sectional view of the display device according to the embodiment.

[00049] With reference to Figure 2, the display panel 100 may include a display unit DU, a touch detection unit TSU, and a color filter layer CFL. The display unit DU may include a substrate SUB, a thin-film transistor layer TFTL, a light-emitting element layer EMTL, and a encapsulation layer TFEL.

[00050] The SUB substrate can be a base substrate or a base member. The SUB substrate can be a flexible substrate that can be flexed, bent, rolled, etc. For example, the SUB substrate can include polymer resin such as polyimide (PI), but the present invention is not limited to this. For another example, the SUB substrate can Petition 870250088599, dated 09 / 30 / 2025, page 52 / 96 11 / 44 include a glass material or a metal material.

[00051] The TFTL thin-film transistor layer can be arranged on the SUB substrate. The TFTL thin-film transistor layer can include a plurality of thin-film transistors that constitute pixel-by-pixel circuits. The TFTL thin-film transistor layer can further include gate lines, DL data lines, power lines, gate control lines, fan-out lines connecting the display driver 200 and the DL data lines, and conductive lines connecting the display driver 200 and the fill units. Each of the thin-film transistors can include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when the sweep driver (e.g., the gate driver) is formed on one side of the non-display NDA area of ​​the display panel 100, this can include thin-film transistors.

[00052] The TFTL thin-film transistor layer can be arranged in the DA display area, the NDA non-display area, and the SBA sub-area. The pixel thin-film transistors, gate lines, DL data lines, and power lines of the TFTL thin-film transistor layer can be arranged in the DA display area. The gate control lines and fan-out lines of the TFTL thin-film transistor layer can be arranged in the NDA non-display area. The driving lines of the TFTL thin-film transistor layer can be arranged in the SBA sub-area.

[00053] The EMTL light-emitting element layer can be arranged on the TFTL thin-film transistor layer. The EMTL light-emitting element layer can include a plurality of light-emitting elements, each including a pixel electrode, a light-emitting layer, and a common electrode sequentially stacked to emit light and a pixel-defining layer that defines the pixels. The light-emitting elements of the light-emitting element layer Petition 870250088599, dated 09 / 30 / 2025, page 53 / 96 12 / 44 EMTL can be placed in the DA display area.

[00054] The light-emitting layer can be an organic light-emitting layer that includes an organic material. The light-emitting layer can include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the pixel electrode receives a predetermined voltage through a thin-film transistor (TFTL) and the common electrode receives a cathodic voltage, holes and electrons can move to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively. Then, the holes and electrons can combine with each other in the organic light-emitting layer to emit light. For example, the pixel electrode can be an anodic electrode, and the common electrode can be a cathodic electrode, but the present invention is not limited to this.

[00055] For another example, each of the light-emitting elements may include a quantum dot light-emitting diode that includes a quantum dot light-emitting layer, an inorganic light-emitting diode that includes an inorganic semiconductor, or a miniature light-emitting diode.

[00056] The TFEL encapsulation layer can cover the top and side surfaces of the EMTL light-emitting element layer and can protect the EMTL light-emitting element layer. The TFEL encapsulation layer can include at least one inorganic layer and at least one organic layer to encapsulate the EMTL light-emitting element layer.

[00057] The TSU touch detection unit can be arranged in the TFEL encapsulation layer. The TSU touch detection unit can include a plurality of touch electrodes to detect a user's touch in a capacitive manner and touch lines that Petition 870250088599, dated 09 / 30 / 2025, page 54 / 96 13 / 44 connect the touch electrodes and the 400 touch driver. For example, the TSU touch detection unit can detect a user touch in a mutual capacitance manner or a self-capacitance manner.

[00058] For another example, the touch detection unit (TSU) can be arranged on a separate substrate located within the display unit (DU). In this case, the substrate supporting the touch detection unit (TSU) can be a base member that encapsulates the display unit (DU).

[00059] The touch electrodes of the TSU touch detection unit can be arranged in a touch sensor area that overlaps the DA display area. The touch lines of the TSU touch detection unit can be arranged in a peripheral touch area that overlaps the non-display NDA area.

[00060] The CFL color filter layer can be arranged in the TSU touch detection unit. The CFL color filter layer can include a plurality of color filters that correspond to a plurality of emission areas, respectively. Each of the color filters can selectively transmit light of a specific wavelength and block or absorb light of other wavelengths. The CFL color filter layer can absorb a portion of the light entering from outside the display device 10, thereby reducing the reflected light caused by external light. Therefore, the CFL color filter layer can prevent color distortion caused by reflecting external light.

[00061] Since the CFL color filter layer is directly placed on the TSU touch detection unit, the display device 10 may not require a separate substrate for the CFL color filter layer. Therefore, the thickness of the display device 10 can be relatively reduced.

[00062] The SBA subarea of ​​display panel 100 can extend Petition 870250088599, dated 09 / 30 / 2025, page 55 / 96 14 / 44 from one side of the main MA area. The SBA subarea may include a flexible material that can be flexed, bent, rolled, etc. For example, if the SBA subarea is flexed, it may be overlapped by the main MA area in the thickness direction (third direction DR3). The SBA subarea may include the display driver 200 and the electrically connected filling units on the circuit board 300.

[00063] Figure 3 is a plan view of a display unit of the display device according to the embodiment. Figure 4 is a block diagram of a display panel and a display driver according to an embodiment.

[00064] With reference to Figures 3 and 4, display panel 100 may include the DA display area and the NDA non-display area.

[00065] The DA display area may include a plurality of PX pixels, a plurality of first-voltage drive lines (VDL) connected to the PX pixels, a plurality of second-voltage drive lines, a plurality of GL gate lines, a plurality of EML emission control lines, and a plurality of DL data lines.

[00066] Each of the PX pixels can be connected to a GL gate line, a DL data line, an EML emission control line, a first drive voltage line (VDL), and a second drive voltage line. Each of the PX pixels can include at least one transistor, one light-emitting element, and one capacitor.

[00067] The GL gate lines can extend in the first direction (DR1) and can be spaced apart in the second direction (DR2) intersecting the first direction (DR1). The GL gate lines can be arranged along the second direction (DR2). The GL gate lines can sequentially provide gate signals to the PX pixels.

[00068] EML emission control lines can extend in the first direction DR1 and can be spaced apart in the second Petition 870250088599, dated 09 / 30 / 2025, pp. 56 / 96 15 / 44 direction DR2. EML emission control lines can be arranged along the second direction DR2. EML emission control lines can sequentially provide emission control signals to the PX pixels.

[00069] DL data lines can extend in the second direction DR2 and can be spaced apart in the first direction DR1. DL data lines can be arranged along the first direction DR1. DL data lines can provide data voltages to PX pixels. The data voltage can determine the luminance of each of the PX pixels.

[00070] The first drive voltage lines (VDL) can extend in the second direction (DR2) and can be spaced apart in the first direction (DR1). The first drive voltage lines (VDL) can be arranged along the first direction (DR1). The first drive voltage lines (VDL) can provide first drive voltages for the PX pixels. The first drive voltages can be high-potential voltages to drive the light-emitting elements of the PX pixels.

[00071] The non-NDA display area may surround the DA display area. The non-NDA display area may include a 610 scan driver, a 620 emission control driver, FL fan-out lines, a first GSL1 port control line, and a second GSL2 port control line.

[00072] The FL fan-out lines can extend from the display driver 200 to the DA display area. The FL fan-out lines can provide data voltages received from the display driver 200 to the DL data lines.

[00073] The first GSL1 port control line can extend from display driver 200 to scan driver 610. The first GSL1 port control line can provide a control signal of Petition 870250088599, dated 09 / 30 / 2025, page 57 / 96 16 / 44 GCS port received from display driver 200 to scan driver 610.

[00074] The second GSL2 port control line can extend from display driver 200 to emission control driver 620. The second GSL2 port control line can provide an ECS emission control signal received from display driver 200 to emission control driver 620.

[00075] The SBA subarea may extend from one side of the non-display NDA area. The SBA subarea may include the display driver 200 and DP filler units. The DP filler units may be arranged closer to one edge of the SBA subarea than the display driver 200. The DP filler units may be electrically connected to the circuit board 300 via an anisotropic conductive film (ACF).

[00076] The display driver 200 may include a timing controller 210 and a data driver 220.

[00077] The timing controller 210 can receive digital video data (DATA) and timing signals from circuit board 300. The timing controller 210 can control the timing operation of data driver 220 by generating a DCS data control signal based on the timing signals, it can control the timing operation of scan driver 610 by generating the GCS gate control signal, and it can control the timing operation of emission control driver 620 by generating the ECS emission control signal. The timing controller 210 can provide the GCS gate control signal to scan driver 610 through the first gate control line GSL1. The timing controller 210 can provide the ECS emission control signal to emission control driver 620 through the second gate control line GSL2. The timing controller 210 can provide the data of Petition 870250088599, dated 09 / 30 / 2025, p. 58 / 96 17 / 44 digital video DATA and DCS data control signal for the 220 data driver.

[00078] The 220 data driver can convert digital video data (DATA) into analog data voltages and supply the analog data voltages to the DL data lines via the FL fanout lines. The 610 scan driver gate signals can select PX pixels to which the data voltages should be supplied, and the selected PX pixels can receive the data voltages via the DL data lines.

[00079] The power supply unit 500 can be arranged on the circuit board 300 to provide power supply voltages for the display driver 200 and the display panel 100. The power supply unit 500 can generate first drive voltages and supply the first drive voltages to the first drive voltage lines VDL, it can generate startup voltages and supply the startup voltages to the startup voltage lines VIL, and it can generate a common voltage and supply the common voltage to the common electrode, common to the light-emitting elements of the PX pixels.

[00080] The scan driver 610 can be arranged outside one side of the display area DA or on one side of the non-display area NDA, and the emission control driver 620 can be arranged outside the other side of the display area DA or on the other side of the non-display area NDA. However, the present invention is not limited to this.For another example, the 610 scan driver and the 620 emission control driver can be arranged on either side of the non-display NDA area.

[00081] The 610 sweep driver may include a plurality of transistors that generate gate signals based on the GCS gate control signal. The 620 emission control driver may include a plurality of transistors that generate emission control signals with Petition 870250088599, dated 09 / 30 / 2025, page 59 / 96 18 / 44 based on the ECS emission control signal. For example, the 610 sweep driver transistors and the 620 emission control driver transistors can be formed in the same layer as the PX pixel transistors. The 610 sweep driver can provide gate signals to the GL gate lines, and the 620 emission control driver can provide emission control signals to the EML emission control lines.

[00082] Figure 5 is an example diagram of a scanning driver according to an embodiment of the present invention.

[00083] With reference to Figure 5, the 610 scan driver, according to the embodiment, includes a plurality of stages that are dependently connected to each other, i.e., n-th stages STn. In the present case, n is a positive integer.

[00084] In Figure 5, for ease of description, only the (n-2)th to the (n+2)th stages STn-2 to STn+2 are illustrated based on an nth stage STn.

[00085] In the following description, a “previous stage” refers to a stage located ahead of the nth stage STn. A “next stage” refers to a stage located behind the nth stage STn. For example, a previous stage of the nth stage STn indicates the (n1)th stage STn-1 and a next stage of the nth stage STn indicates the (n+1)th stage STn+1.

[00086] The sweep clock lines and detection control lines can be arranged on one side from the (n-2)th to the (n+2)th stages STn-2 to STn+2. A plurality of sweep clock signals CLK1 and CLK2 whose phases are sequentially delayed or alternated are applied to the sweep clock lines, respectively, and a start signal ST, a line selection signal ES, and a reset signal are transmitted to the detection control lines, respectively. Petition 870250088599, dated 09 / 30 / 2025, p. 60 / 96 19 / 44

[00087] The CLK1 and CLK2 scan clock signals, the ES line selection signal, the ST start signal, and the reset signal can be GCS gate control signals generated from the 200 display driver and transmitted through the first GSL1 gate control lines. In Figure 5, the two scan clock lines, two detection control lines, and two power lines are illustrated as the first GSL1 gate control lines. However, the number of scan clock lines and detection control lines is not limited to this.

[00088] The 610 scan driver includes the (n-2)th to (n+2)th STn-2 to STn+2 stages connected to the first GSL1 gate control lines, respectively. Among the nth STn stages, the (n2)th STn-2 stage emits an (n-2)th SCn-2 scan signal to an (n-2)th SCLn-2 scan signal line, and the (n-1)th STn-1 stage emits an (nl)th SCn-1 scan signal to an (nl)th SCLn-1 scan signal line. Consequently, the nth STn stage can emit an nth SCn scan signal to an nth SCLn scan signal line. Next, the (n+1)th stage STn+1 emits an (n+1)th sweep signal SCn+1 to an (n+1)th sweep signal line SCLn+1, and the (n+2)th stage STn+2 emits an (n+2)th sweep signal SCn+2 to an (n+2)th sweep signal line SCLn+2.

[00089] Each of the (n-2)th to (n+2)th stages STn-2 to STn+2 includes a previous loading terminal CPI, a next loading terminal CNI, a first scan clock terminal SCI1, a second scan clock terminal SCI2, a first power supply terminal SSI1, a second power supply terminal SSI2, a detection signal terminal RSI, and a scan output terminal SCO.

[00090] When the (n-2)th stage STn-2 is a first stage, Petition 870250088599, dated 09 / 30 / 2025, p. 61 / 96 20 / 44 The ST start signal can be entered into the CPI upstream loading terminal of the (n-2)th stage STn-2 via a start signal line. The CPI upstream loading terminal of each of the dependently connected stages except the first stage can be connected to the SCO scan output terminal of the immediately preceding stage. For example, as illustrated in Figure 5, the CPI upstream loading terminal of the nth stage STn can be connected to the SCO scan output terminal of the (n-1)th stage STn-1.

[00091] The next CNI loading terminal of each of the (n-2)th to (n+2)th stages STn-2 to STn+2 can be connected to the SCO scan output terminal of any next stage. For example, as illustrated in Figure 5, the next CNI loading terminal of the nth stage STn can be connected to the SCO scan output terminal of the (n+1)th stage STn+1 and can receive the SCn+1 scan signal from the (n+1)th stage STn+1 as a next loading signal.

[00092] The SCO scan output terminals of the (n-2)th to (n+2)th stages STn-2 to STn+2 are sequentially connected to the SCL scan signal lines, which are corresponding GL gate lines, respectively. Consequently, each of the SCL scan signal lines can be connected one by one to the SCO scan output terminals of all stages STn-2 to STn+2. For example, the (n1)th SCL scan signal line n-1 is connected to the SCO scan output terminal of the (n1)th stage STn-1, and the nth SCL scan signal line n is connected to the SCO scan output terminal of the nth stage STn. Furthermore, the (n+1)th SCL scan signal line n+1 can be connected to the SCO scan output terminal of the (n+1)th stage STn+1.

[00093] The RSI detection signal terminal of each of the (n Petition 870250088599, dated 09 / 30 / 2025, p. 62 / 96 21 / 44 2)th to (n+2)th stages STn-2 to STn+2 receive the line selection signal ES through a detection control line to which the line selection signal ES is transmitted.

[00094] Each of the (n-2)th to (n+2)th stages STn-2 to STn+2 receives two sweep clock signals, namely, first and second sweep clock signals CLK1 and CLK2 whose phases are sequentially alternated or delayed through the first sweep clock terminal SCI1 and the second sweep clock terminal SCI2.

[00095] For example, each of the (n-2)th to (n+2)th stages STn-2 to STn+2 can receive the first sweep clock signal CLK1 to the first sweep clock terminal SCI1 and receive the second sweep clock signal CLK2 whose phase is sequentially alternated or delayed from the first sweep clock signal CLK1 to the second sweep clock terminal SCI2.

[00096] The (n-2)th to (n+2)th stages STn-2 to STn+2 sequentially transmit the SCn-2 to SCn+2 scan signals to the SCLn-2 to SCLn+2 scan signal lines connected one by one through their respective SCO scan output terminals, respectively. For example, during at least one frame period, the (n-2)th stage STn-2 transmits the (n-2)th SCn-2 scan signal to the (n-2)th SCLn-2 scan signal line connected to the SCO scan output terminal. Then, the (n-1)th stage STn-1 transmits the (nl)th SCn-1 scan signal to the (nl)th SCLn-1 scan signal line connected to the SCO scan output terminal. Consequently, the nth stage STn emits the nth scan signal SCn to the nth scan signal line SCLn connected to the scan output terminal SCO.Subsequently, the (n+1)th stage STn+1 can emit the (n+1)th sweep signal SCn+1 to the (n+1)th sweep signal line SCLn+1 connected to. Petition 870250088599, dated 09 / 30 / 2025, p. 63 / 96 22 / 44 SCO scan output terminal, and the (n+2)th stage STn+2 can output the (n+2)th scan signal SCn+2 to the (n+2)th scan signal line SCLn+2 connected to the SCO scan output terminal.

[00097] In general, the 610 scan driver can be composed of ST1 to STn stages that sequentially emit first to nth SC1 to SCn scan signals for each active period during each frame period. The specific structure of the 610 scan driver has been described using Figure 5.

[00098] The 620 emission control driver, which sequentially generates and emits emission signals in response to the ECS emission control signal received from the 200 display driver, can also be constructed to include the (n-2)th to (n+2)th stages STn-2 to STn+2, i.e., the nth stages STn. Therefore, a detailed description of the structure of the 620 emission control driver will be replaced by a description of the 610 scanning driver.

[00099] Figure 6 is a detailed circuit diagram of a first embodiment of an nth stage of the sweep driver illustrated in Figure 5. In particular, Figure 6 illustrates the nth stage STn among the (n-2)th to (n+2)th stages STn-2 to STn+2 as an example. [000100] The nth stage STn includes an output node controller SCC and an output controller OUC. In addition, the nth stage STn also includes a first power supply terminal SSI1 to which a gate activation voltage VGH is supplied, and a second power supply terminal SSI2 to which a gate deactivation voltage VGL is supplied. [000101] The nth stage STn can operate in response to the ST start signal received through the previous charging terminal CPI. However, when connected dependently to the (n-1)th stage Petition 870250088599, dated 09 / 30 / 2025, p. 64 / 96 23 / 44 Previously, the nth STn stage can operate in response to the (n1)th SCn-1 sweep signal from the (n-1)th STn-1 stage received as a load signal. An example where the nth STn stage is any nth STn stage that is dependently connected to the previous (nl)th STn-1 stage will be described below. [000102] The nth stage SCC output node controller STn enables the output controller OUC by providing a voltage at the same level as the VGH gate activation voltage to a load node Q during the active period of each frame period. While the load node Q is held at the VGH gate activation voltage level, the VGL gate deactivation voltage from the second power supply terminal SSI2 is applied to a discharge node QB. [000103] Specifically, the SCC output node controller provides the gate activation voltage VGH to the load node Q in response to the line selection signal ES inserted during the active period or a loading signal from a previous stage, i.e., the (n1)th sweep signal SCn-1 of the (n-1)th stage STn-1. In this document, the line selection signal ES or the loading signal from the previous stage may be at the gate activation voltage level. When the gate activation voltage VGH is applied to the load node Q of the SCC output node controller, the load node Q of the SCC output node control unit is enabled according to the level of the gate activation voltage VGH. The SCC output node controller controls the gate deactivation voltage VGL to be supplied to the discharge node QB during a period when the gate activation voltage VGH is applied to the load node Q. [000104] When the load node Q of the output node controller SCC is enabled, the output controller OUC emits the nth scan signal SCn to the nth scan signal line SCLn connected to the scan output terminal SCO in response to any signal. Petition 870250088599, dated 09 / 30 / 2025, pp. 65 / 96 24 / 44 CLK2 sweep clock signals from CLK1 and CLK2 sweep clock signals. [000105] After the nth SCn scan signal is emitted, the output node controller SCO controls the VGL gate disable voltage to be supplied to the load node Q in response to either a CLK1 scan clock signal from the CLK1 and CLK2 scan clock signals or the (n+1)th SCn+1 scan signal from the (n+1)th STn+1 stage. The load node Q is disabled by the VGL gate disable voltage. [000106] The output node controller SCC enables the discharge node QB with the gate activation voltage VGH in response to either the CLK1 sweep clock signal or the CLK1 and CLK2 sweep clock signals during a period when the load node Q is disabled. [000107] When the QB discharge node of the SCC output node controller is enabled, the OUC output controller electrically connects the nth scan signal line SCLn to the second power supply terminal SSI2 to which the VGL gate disable voltage is applied. [000108] The (n-2)th to (n+2)th stages STn-2 to STn+2 emit the nth SCn sweep signals to their respective SCLn sweep signal lines and sequentially and repeatedly perform an operation to hold their respective SCLn sweep signal lines at the VGL gate disable voltage. [000109] The nth stage SCC output node controller STn may include the first to seventh transistors T1 to T7 and at least one first capacitor C1. Either of the first and second electrodes of each of the first to seventh transistors T1 to T7 may be a source electrode, and the other may be a drain electrode. [000110] Specifically, a gate electrode of the first transistor Petition 870250088599, dated 09 / 30 / 2025, pp. 66 / 96 25 / 44 T1 can be connected to the load node Q, the first electrode of the first transistor T1 can be connected to the second clock sweep terminal SCI2, and the second electrode of the first transistor T1 can be connected to the previous load terminal CPI and to the first electrode of the second transistor T2. The first transistor T1 can be activated when the load node Q is enabled by the gate activation voltage VGH and can supply the second clock sweep terminal SCI2 to the first capacitor C1 and the second transistor T2 connected in parallel. [000111] A gate electrode of the second transistor T2 is connected to the discharge node QB, and the first electrode of the second transistor T2 is connected to the second electrode of the first transistor T1 and to the front charging terminal CPI. Additionally, the second electrode of the second transistor T2 is connected to the second power supply terminal SSI2. The second transistor T2 is activated when the discharge node QB is enabled by the gate activation voltage VGH and supplies the gate deactivation voltage VGL to the first transistor T1. [000112] A gate electrode of the third transistor T3 is connected to the load node Q, and the first electrode of the third transistor T3 is connected to the first sweep clock terminal SCI1. Additionally, the second electrode of the third transistor T3 is connected to the discharge node QB. The third transistor T3 can be activated when the load node Q is enabled by the gate activation voltage VGH and can provide the first sweep clock signal CLK1 to the discharge node QB. [000113] One gate electrode of the fourth transistor T4 is connected to the sensing signal terminal RSI or the front load terminal CPI, and the first electrode of the fourth transistor T4 is connected to the first power supply terminal SSI1. Additionally, the second electrode of the fourth transistor T4 is connected to the load node Q. The fourth Petition 870250088599, dated 09 / 30 / 2025, pp. 67 / 96 26 / 44 transistor T4 is activated in response to the ES line selection signal from the RSI sensing signal terminal or the previous load signal and provides the VGH gate activation voltage to the load node Q. Consequently, the fourth transistor T4 can enable the load node Q at the VGH gate activation voltage level in response to the ES line selection signal from the RSI sensing signal terminal or the previous load signal. [000114] One gate electrode of the fifth transistor T5 is connected to the first sweep clock terminal SC11, and the first electrode of the fifth transistor T5 is connected to the first power supply terminal SSI1. Additionally, the second electrode of the fifth transistor T5 is connected to the discharge node QB. The fifth transistor T5 is activated in response to the first sweep clock signal CLK1 and provides gate activation voltage VGH to the discharge node QB. Consequently, the fifth transistor T5 can enable the discharge node QB at the gate activation voltage level VGH in response to the first sweep clock signal CLK1. [000115] A gate electrode of the sixth transistor T6 is connected to the second clock sweep terminal SCI2, and the first electrode of the sixth transistor T6 is connected to the load node Q. Furthermore, the second electrode of the sixth transistor T6 is connected to the second electrode of the first transistor T1 or to the first electrode of the seventh transistor T7. Consequently, the sixth transistor T6 electrically connects the load node Q to the second electrode of the first transistor T1 or the first electrode of the seventh transistor T7 in response to the second clock sweep terminal SCI2. The sixth transistor T6 can serve as a diode between the load node Q and the first capacitor C1. [000116] A gate electrode of the seventh transistor T7 is connected to the discharge node QB, and the first electrode of the seventh transistor T7 is connected to the second electrode of the sixth transistor T6. Furthermore, the Petition 870250088599, dated 09 / 30 / 2025, pp. 68 / 96 27 / 44 The second electrode of the seventh transistor T7 is connected to the second electrode of the first transistor T1 and to the first capacitor C1. The seventh transistor T7 is activated when the discharge node QB is enabled and electrically connects the second electrode of the sixth transistor T6 to the first capacitor C1 and to the second electrode of the first transistor T1. The seventh transistor T7 acts as a diode to keep the sixth transistor T6 and the first transistor T1 deactivated during the enabling period of the discharge node QB. [000117] The OUC output controller includes a DT load transistor and a VT discharge transistor. [000118] The load transistor DT has a first electrode connected to the second sweep clock terminal SCI2, a gate electrode connected to the load node Q, and a second electrode connected to the sweep output terminal SCO. The load transistor DT is activated by the gate activation voltage VGH from the load node Q and outputs any sweep clock signal fed into the second sweep clock terminal SCI2, for example, the second sweep clock signal CLK2 at the sweep output terminal SCO. Consequently, the nth sweep signal SCn from the gate activation voltage can be fed to the nth sweep signal line SCLn. [000119] The discharge transistor VT may have a first electrode connected to the SCO sweep output terminal, a gate electrode connected to the discharge node QB, and a second electrode connected to the second power supply terminal SSI2. The discharge transistor VT is activated by the gate activation voltage VGH from the discharge node QB and transmits the gate deactivation voltage VGL inserted at the second power supply terminal SSI2 to the SCO sweep output terminal. Therefore, the nth sweep signal line SCLn connected to the SCO sweep output terminal can be maintained at the gate deactivation voltage level VGL during the period Petition 870250088599, dated 09 / 30 / 2025, pp. 69 / 96 28 / 44 activation of the discharge transistor VT. [000120] Figure 7 is a waveform diagram illustrating changes in voltage levels of detection control signals, sweep clock signals, and a load node during an active period of an Nth-frame period. [000121] With reference to Figure 7, the line selection signal ES, the start signal ST, and the first and second sweep clock signals CLK1 and CLK2 are signals that are generated at the gate activation voltage level VGH during a horizontal period 1H. The line selection signal ES can be generated every horizontal period 1H so that the gate activation voltage VGH can be supplied to the load node Q of each of the stages STn-2 to STn+2 during the active period. Even if the line selection signal ES is not generated and supplied, it can be replaced by the start signal ST or a load signal from a previous stage (i.e., a previous load signal). [000122] The first and second CLK1 and CLK2 sweep clock signals are clock signals whose phases are sequentially delayed or repeatedly alternated. Each of the first and second CLK1 and CLK2 sweep clock signals can be generated at the VGH gate activation voltage level for at least one horizontal period 1H and can be generated at the VGL gate deactivation voltage level for at least one horizontal period 1H. In this document, the generation period, pulse width, and amplitude of each of the first and second CLK1 and CLK2 sweep clock signals are not limited to those in Figure 7 and can be variably altered. [000123] The gate activation voltage VGH may be the high gate voltage that can activate transistors included in each of the (n-2)th to (n+2)th stages STn-2 to STn+2 of the driver. Petition 870250088599, dated 09 / 30 / 2025, pp. 70 / 96 29 / 44 sweep 610 and PX subpixel transistors. The gate disable voltage VGH can be the low gate voltage VGL which can disable the transistors from the (n-2)th to the (n+2)th stages STn-2 to STn+2 of the 610 sweep driver and the PX subpixel transistors. [000124] The operation of the nth stage STn during any frame will be briefly described below with reference to Figures 6 and 7. [000125] First, the fourth transistor T4 is activated in response to the line selection signal ES from the RSI sensing signal terminal or the ST start signal and provides the gate activation voltage VGH to the load node Q. Consequently, the load node Q is enabled. [000126] Next, the first transistor T1 is activated when the load node Q is enabled by the gate activation voltage VGH and charges the first capacitor C1. Furthermore, the load transistor DT is activated by the gate activation voltage VGH from the load node Q and outputs the second sweep clock signal CLK2, which is fed into the second sweep clock terminal SCI2, to the sweep output terminal SCO. Consequently, the load node Q is self-high and the nth sweep signal SCn from the gate activation voltage VGH is supplied to the nth sweep signal line SCLn. [000127] After that, the fifth transistor T5 is activated in response to the first sweep clock signal CLK1 and enables the discharge node QB at the gate activation voltage level VGH. The discharge transistor VT is activated by the gate activation voltage VGH of the discharge node QB and transmits the gate deactivation voltage VGL inserted at the second power supply terminal SSI2 to the sweep output terminal SCO. Therefore, the nth sweep signal line SCLn connected to the sweep output terminal SCO can be maintained at the gate deactivation voltage level VGL during the activation period of the discharge transistor VT. Petition 870250088599, dated 09 / 30 / 2025, pp. 71 / 96 30 / 44 [000128] Figure 8 is a detailed circuit diagram of a second embodiment of the nth stage of the sweep driver illustrated in Figure 5. [000129] With reference to Figure 8, an SCC output node controller of the nth stage STn may further include an eighth transistor T8 that disables a load node Q with a gate disable voltage VGL in response to an upcoming load signal from a next STn+1 stage. [000130] A gate electrode of the eighth transistor T8 is connected to a nearby charging terminal CNI, and a first electrode of the eighth transistor T8 is connected to a previous charging terminal CPI or a second power supply terminal SSI2. Additionally, a second electrode of the eighth transistor T8 is connected to the charging node Q. Consequently, the eighth transistor T8 can supply the gate turn-off voltage VGL to the charging node Q in response to the next charging signal from the next stage STn+1. [000131] As described above, the SCC output node controllers of all stages, i.e., the (n-2)th to (n+2)th stages STn-2 to STn+2, may each include the first to seventh transistors T1 to T7 or the first to eighth transistors T1 to T8. At least one of the first to eighth transistors T1 to T8 of each STn stage, for example, the first transistor T1, the third transistor T3, and the fourth transistor T4, enable the load node Q using the gate activation voltage VGH and, during a period when the enabled load node Q is self-raised to a voltage greater than the gate activation voltage VGH by a CLK2 sweep clock signal, receive the self-raised voltage across either electrode. Consequently, the first, third, and fourth transistors T1, T3, and T4 may be subjected to high potential and high voltage stress, and the current and voltage characteristics as limiting voltage characteristics of their Petition 870250088599, dated 09 / 30 / 2025, p. 72 / 96 31 / 44 semiconductor layers (or active layers) can be altered by the influence of high potential and high voltage stress. If the current and voltage characteristics of the first, third, and fourth transistors T1, T3, and T4 are altered, the current and voltage output characteristics of the first, third, and fourth transistors T1, T3, and T4 may deteriorate, thus reducing the output of each of the STn-2 to STn+2 stages or decreasing reliability. [000132] In this sense, the semiconductor layer (or active layer) of at least one of the first to eighth transistors T1 to T8 of each STn stage may be made of a different oxide semiconductor material than the semiconductor layer (or active layer) of at least one other transistor T1 to T8. [000133] For example, the semiconductor layer (or active layer) of at least one transistor T1 to T8 that is directly connected to the load node Q and subjected to high potential and high voltage stress among the first to eighth transistors T1 to T8 of each STn stage may include a different oxide semiconductor material than the semiconductor layer (or active layer) of at least one other transistor T1 to T8 that is not directly connected to the load node Q. [000134] In particular, the semiconductor layers (or active layers) of the first, third, and fourth transistors T1, T3, and T4 directly connected to the load node Q among the first to eighth transistors T1 to T8 of each STn stage can be made of a different oxide semiconductor material that increases (?) a range of current quantity. Consequently, the current quantity and current transfer rate of the first, third, and fourth transistors T1, T3, and T4 can be increased. [000135] Figure 9 is a cross-sectional view illustrating the cross-sectional structure of the first and sixth transistors of the sweep driver illustrated in Figure 8. Petition 870250088599, dated 09 / 30 / 2025, p. 73 / 96 32 / 44 [000136] With reference to Figures 8 and 9, at least one transistor indirectly connected to the load node Q, for example, the second and fifth to seventh transistors T2, T5, T6 and T7 among a plurality of transistors T1 to T8 included in each STn stage include an active first layer ACT1 which includes an oxide semiconductor. [000137] On the other hand, at least one transistor directly connected to the load node Q, for example, the first, third, fourth and eighth transistors T1, T3, T4 and T8 among the transistors T1 to T8 included in each STn stage include a second active layer ACT2 that includes a different oxide semiconductor than the oxide semiconductor of the first active layer ACT1. [000138] Specifically, a BR barrier layer is formed on the SUB substrate where each STn stage is formed, and the TFTL thin-film transistor layer which includes a plurality of T1 to T8 transistors from each STn stage is formed on the BR barrier layer. [000139] The SUB substrate can be a rigid substrate or a flexible substrate that can be flexed, bent, or rolled. The SUB substrate can be made of an insulating material such as glass, quartz, or polymer resin. The polymer material can be, for example, polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyalylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or a combination thereof. Alternatively, the SUB substrate may include a metal material. [000140] The BR barrier layer can be disposed on the SUB substrate. The BR barrier layer can be a layer to protect the TFTL thin-film transistor layer from moisture introduced through the SUB substrate, which is vulnerable to moisture penetration. The BR barrier layer can be composed of a plurality of Petition 870250088599, dated 09 / 30 / 2025, pp. 74 / 96 33 / 44 inorganic layers stacked alternately. For example, the BR barrier layer can be a multilayer in which one or more inorganic layers selected from a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are stacked alternately. [000141] The TFTL thin-film transistor layer, which includes a plurality of transistors T1 to T8 from each STn stage, is formed in the BR barrier layer. [000142] The TFTL thin-film transistor layer of at least one transistor indirectly connected to the load node Q, for example, the TFTL thin-film transistor layer of the sixth transistor T6 includes a first gate electrode GEb1, an interlayer insulating layer BF, the first active layer ACT1, first and second gate insulating layers GTI1 and GTI2, and a second gate electrode GE6. [000143] The BF interlayer insulating layer is formed to cover the BR barrier layer as well as the first gate electrode GEb1. [000144] The first active layer ACT1 is formed to cover the first gate electrode GEb1 with the interlayer insulating layer BF interposed between them, thus forming a sixth channel region CH6. A first electrode E61 and a second electrode E62 can be defined on one side and the other side of the first active layer ACT1, respectively. [000145] The first insulating layer of gate GTI1 is formed to overlap the first gate electrode GEb1 with the first active layer ACT1 interposed between them, and the second insulating layer of gate GTI2 is formed to overlap the first gate electrode GEb1 with the first insulating layer of gate GTI1 interposed between them. Petition 870250088599, dated 09 / 30 / 2025, pp. 75 / 96 34 / 44 [000146] The second GE6 gate electrode is formed to overlap the first GEb1 gate electrode with the first and second GTI1 and GTI2 gate insulating layers interposed between them. [000147] The BF interlayer insulating layer may include an inorganic layer, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The BF interlayer insulating layer may include a plurality of inorganic layers. [000148] The first active ACT1 layer may include polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor material. When the first active ACT1 layer includes an oxide semiconductor material, it may include indium gallium zinc oxide (IGZO). [000149] When the first active ACT1 layer includes polycrystalline silicon or an oxide semiconductor material, a source region and a drain region in the first active ACT1 layer can be ion-doped conductive regions to have conductivity. [000150] The first insulating layer of GTI1 gate may include at least one of tetraethyl orthosilicate (TEOS), silicon nitride (SiNx), and silicon oxide (SiO2). For example, the first insulating layer of GTI1 gate may have a double-layer structure in which a 40 nm thick silicon nitride layer and an 80 nm thick tetraethyl orthosilicate layer are stacked sequentially. The second insulating layer of GTI2 gate may include the same material and structure as the first insulating layer of GTI1 gate described above. [000151] Meanwhile, at least one transistor directly connected to the load node Q, for example, the first, third, fourth and eighth transistors T1, T3, T4 and T8 among the transistors T1 to T8 included Petition 870250088599, dated 09 / 30 / 2025, pp. 76 / 96 35 / 44 in each STn stage include a second active layer ACT2 that includes a different oxide semiconductor than the oxide semiconductor of the first active layer ACT1. [000152] For example, the TFTL thin-film transistor layer of the first transistor T1 directly connected to the load node Q includes a first gate electrode GEb1, the interlayer insulating layer BF, the second active layer ACT2, the first and second gate insulating layers GTI1 and GTI2, and a second gate electrode GE5. [000153] The BF interlayer insulating layer is formed to cover the BR barrier layer as well as the first gate electrode GEb1. [000154] The second active layer ACT2 is formed to cover the first gate electrode GEb1 with the interlayer insulating layer BF interposed between them, thus forming a first channel region CH1. A first electrode E61 and a second electrode E62 can be defined on one side and the other side of the second active layer ACT2, respectively. [000155] The first insulating layer of the GTI1 gate is formed to overlap the first gate electrode of GEb1 with the second active layer of ACT2 (or the interlayer insulating layer of BF) interposed between them, and the second insulating layer of the GTI2 gate is formed to overlap the first gate electrode of GEb1 with the first insulating layer of the GTI1 gate (or the second active layer of ACT2) interposed between them. [000156] The second GE6 gate electrode is formed to overlap the first GEb1 gate electrode with the first and second insulating layers of GTI1 and GTI2 gates (or the second insulating layer of GTI2 gates and the second active layer ACT2) interposed between them. [000157] The second active layer ACT2 may include a different oxide semiconductor material than the first active layer ACT1. By Petition 870250088599, dated 09 / 30 / 2025, pp. 77 / 96 36 / 44 For example, when the first active layer ACT1 is an oxide semiconductor that includes indium gallium zinc oxide (IGZO), the second active layer ACT2 can be an oxide semiconductor that includes indium gallium zinc tin oxide (IGZTO). When the second active layer ACT2 includes a different oxide semiconductor material than the first active layer ACT1, a source region and a drain region in the second active layer ACT2 can be ion-doped conductive regions to have conductivity. [000158] Since the first active layer ACT1 and the second active layer ACT2 are semiconductor layers made of different materials, they can be formed on the SUB substrate through different processes. [000159] The second and fifth to seventh transistors T2 and T5 to T7, which require high switching speed, may include the first active layer ACT1 made of indium gallium zinc oxide (IGZO). [000160] However, the first, third, fourth, and eighth transistors T1, T3, T4, and T8, which require a wide current transfer range and high reliability, may include the second active layer ACT2 made of indium gallium zinc tin oxide (IGZTO). In other words, the first, third, fourth, and eighth transistors T1, T3, T4, and T8, which are directly connected to the load node Q and require high reliability, may include a different oxide semiconductor material than the first, third, fourth, and eighth transistors T1, T3, T4, and T8. Consequently, both high reliability and high speed can be satisfied for each STn stage. [000161] Figure 10 is a diagram of another embodiment of an nth stage of the sweep driver illustrated in Figure 8. In addition, Figure 11 is a cross-sectional view illustrating the cross-sectional structure of the fourth and sixth transistors of the sweep driver illustrated in Figure 10. Petition 870250088599, dated 09 / 30 / 2025, pp. 78 / 96 37 / 44 [000162] With reference to Figures 10 and 11, the fourth transistor T4 directly connected to the load node Q, among the transistors T1 to T8 included in each STn stage, may include a second active layer ACT2 that includes a different oxide semiconductor than the oxide semiconductor of the first active layer ACT1. [000163] On the other hand, the second and fifth to seventh transistors T2, T5, T6 and T7 indirectly connected to the load node Q among the transistors T1 to T8 included in each STn stage may include the first active layer ACT1 which includes an oxide semiconductor. [000164] The TFTL thin-film transistor layer of the fourth transistor T4 directly connected to the load node Q may include a first gate electrode GEb1, the interlayer insulating layer BF, the second active layer ACT2 forming a fourth channel region CH4, the first and second gate insulating layers GTI1 and GTI2, and a second gate electrode GE4. [000165] The BF interlayer insulating layer is formed to cover the BR barrier layer as well as the first gate electrode GEb1, and the second active layer ACT2 is formed to cover the first gate electrode GEb1 with the BF interlayer insulating layer interposed between them, thus forming the fourth channel region CH4. [000166] The first insulating layer of gate GTI1 is formed to overlap the first gate electrode GEb1 with the second active layer ACT2 interposed between them, and the second insulating layer of gate GTI2 is formed to overlap the first gate electrode GEb1 with the first insulating layer of gate GTI1 interposed between them. [000167] The second GE6 gate electrode is formed to overlap the first GEb1 gate electrode with the first and second insulating layers of GTI1 and GTI2 gates interposed between them, and a Petition 870250088599, dated 09 / 30 / 2025, p. 79 / 96 38 / 44 The first electrode E61 and a second electrode E62 can be placed on one side and the other side of the second active layer ACT2, respectively. [000168] The second active layer ACT2 of the fourth transistor T4 includes a different oxide semiconductor material than the first active layer ACT1. The second active layer ACT2 may be an oxide semiconductor that includes indium gallium zinc tin oxide (IGZTO). [000169] Among the transistors T1 to T8 included in each STn stage, the third and fourth transistors T3 and T4 directly connected to the load node Q may include the second active layer ACT2 which includes a different oxide semiconductor than the first active layer ACT1, and the first transistor T1 directly connected to the load node Q may include the first active layer ACT1 which includes an oxide semiconductor. [000170] Alternatively, among the transistors T1 to T8 included in each STn stage, the first transistor T1 directly connected to the load node Q may include the second active layer ACT2 which includes a different oxide semiconductor than the first active layer ACT1, and the third and fourth transistors T3 and T4 directly connected to the load node Q may include the first active layer ACT1 which includes an oxide semiconductor. The fifth transistor T5 may include the second active layer ACT2 which includes a different oxide semiconductor than the first active layer ACT1. [000171] The discharge transistor VT of the OUC output controller may include the first active layer ACT1 which includes an oxide semiconductor. On the other hand, the load transistor DT of the OUC output controller which is directly connected to the load node Q may include the second active layer ACT2 which includes a different oxide semiconductor material than the first active layer ACT1 of the discharge transistor VT. [000172] Figures 12 and 13 are perspective views of an example application of a display device according to a Petition 870250088599, dated 09 / 30 / 2025, pp. 80 / 96 39 / 44 embodiment of the present invention. [000173] Figures 12 and 13 illustrate an example where the display device 10 is applied as a foldable display device that is folded in a first direction (geometric axis X direction). The display device 10 can maintain both a folded and an unfolded state. The display device 10 can be folded in an inward folding manner where a front surface is arranged on the inside. When the display device 10 is flexed or folded in the inward folding manner, portions of the front surface of the display device 10 can be facing each other. Alternatively, the display device 10 can be folded in an outward folding manner where the front surface is arranged on the outside.When the display device 10 is flexed or folded in the outward folding manner, portions of a front rear surface of the display device 10 can be faced toward each other. [000174] A first non-folding area NFA1 may be arranged on one side, for example, the right side of a folding area FDA. A second non-folding area NFA2 may be arranged on the other side, for example, the left side of the folding area FDA. A touch detection unit TSU according to an embodiment of this descriptive report may be formed and arranged in each of the first non-folding area NFA1 and the second non-folding area NFA2. [000175] A first folding line FOL1 and a second folding line FOL2 can extend in a second direction (Y-axis geometric direction), and the display device 10 can be folded in the first direction (X-axis geometric direction). Therefore, since a length of the display device 10 in the first direction (X-axis geometric direction) can be reduced almost by Petition 870250088599, dated 09 / 30 / 2025, pp. 81 / 96 40 / 44 half, a user can easily charge the display device 10. [000176] The direction in which the first folding line FOL1 and the second folding line FOL2 extend is not limited to the second direction (Y-axis geometric direction). For example, the first folding line FOL1 and the second folding line FOL2 can also extend in the first direction (X-axis geometric direction), and the display device 10 can also be folded in the second direction (Y-axis geometric direction). In this case, the length of the display device 10 in the second direction (Y-axis geometric direction) can be reduced by almost half. Alternatively, the first folding line FOL1 and the second folding line FOL2 can extend in a diagonal direction of the display device 10 between the first direction (X-axis geometric direction) and the second direction (Y-axis geometric direction). In this case, the display device 10 can be folded into a triangular shape. [000177] When the first fold line FOL1 and the second fold line FOL2 extend in the second direction (Y-axis geometric direction), the length of the fold area FDA in the first direction (X-axis geometric direction) can be less than the length of the fold area FDA in the second direction (Y-axis geometric direction). Furthermore, the length of the first unfolded area NFA1 in the first direction (X-axis geometric direction) can be greater than the length of the fold area FDA in the first direction (X-axis geometric direction). The length of the second unfolded area NFA2 in the first direction (X-axis geometric direction) can be greater than the length of the fold area FDA in the first direction (X-axis geometric direction). [000178] A first display area DA1 can be arranged in front of the display device 10. The first display area DA1 Petition 870250088599, dated 09 / 30 / 2025, pp. 82 / 96 41 / 44 can overlap the FDA folding area, the first non-folding area NFA1, and the second non-folding area NFA2. Therefore, when display device 10 is unfolded, an image can be displayed forward in the FDA folding area, the first non-folding area NFA1, and the second non-folding area NFA2 of display device 10. [000179] A second display area DA2 can be arranged on the rear of the display device 10. The second display area DA2 can overlap the second non-folding area NFA2. Therefore, when the display device 10 is folded, an image can be displayed forward on the second non-folding area NFA2 of the display device 10. [000180] In Figures 12 and 13, a TH through hole in which an SDA camera is formed is arranged in the first non-folding area NFA1. However, the present invention is not limited to this. The TH through hole or the SDA camera can also be arranged in the second non-folding area NFA2 or in the folding area FDA. [000181] Figures 14 and 15 are perspective views of an example application of a display device according to another embodiment of the present invention. [000182] Figures 14 and 15 illustrate an example where the display device 10 is applied as a foldable display device that is folded in a second direction (Y-axis geometric direction). The display device 10 can maintain both a folded and an unfolded state. The display device 10 can be folded in an inward folding manner where a front surface is disposed on the inside. When the display device 10 is flexed or folded in the inward folding manner, portions of the front surface of the display device 10 can be Petition 870250088599, dated 09 / 30 / 2025, pp. 83 / 96 42 / 44 facing each other. Alternatively, the display device 10 can be folded in an outward folding manner whereby the front surface is positioned on the outside. When the display device 10 is flexed or folded in the outward folding manner, portions of a front rear surface of the display device 10 can face each other. [000183] The display device 10 may include an FDA folding area, a first non-folding area NFA1, and a second non-folding area NFA2. The FDA folding area may be an area where the display device 10 is folded, and the first non-folding area NFA1 and the second non-folding area NFA2 may be areas where the display device 10 is not folded. The first non-folding area NFA1 may be located on one side, for example, a lower side of the FDA folding area. The second non-folding area NFA2 may be located on the other side, for example, an upper side of the FDA folding area. [000184] A TSU touch detection unit according to an embodiment of the present descriptive report may be formed and arranged in each of the first non-folding area NFA1 and the second non-folding area NFA2. [000185] The FDA folding area can be an area that is bent with a predetermined curvature in a first folding line FOL1 and a second folding line FOL2. Therefore, the first folding line FOL1 can be a boundary between the FDA folding area and the first non-folding area NFA1, and the second folding line FOL2 can be a boundary between the FDA folding area and the second non-folding area NFA2. [000186] The first folding line FOL1 and the second folding line FOL2 can extend in a first direction (geometric axis X direction) as illustrated in Figures 14 and 15, and the Petition 870250088599, dated 09 / 30 / 2025, pages 84 / 96 The 43 / 44 display device 10 can be folded in the second direction (Y-axis geometric direction). Therefore, since the length of the display device 10 in the second direction (Y-axis geometric direction) can be reduced by almost half, a user can easily carry the display device 10. [000187] The direction in which the first folding line FOL1 and the second folding line FOL2 extend is not limited to the first direction (X-axis geometric direction). For example, the first folding line FOL1 and the second folding line FOL2 can also extend in the second direction (Y-axis geometric direction), and the display device 10 can also be folded in the first direction (X-axis geometric direction). In this case, the length of the display device 10 in the first direction (X-axis geometric direction) can be reduced by almost half. Alternatively, the first folding line FOL1 and the second folding line FOL2 can extend in a diagonal direction of the display device 10 between the first direction (X-axis geometric direction) and the second direction (Y-axis geometric direction). In this case, the display device 10 can be folded into a triangular shape. [000188] When the first fold line FOL1 and the second fold line FOL2 extend in the first direction (geometric axis X direction) as illustrated in Figures 14 and 15, a fold area length FDA in the second direction (geometric axis Y direction) can be shorter than a fold area length FDA in the first direction (geometric axis X direction). Furthermore, a length of the first unfolded area NFA1 in the second direction (geometric axis Y direction) can be longer than the fold area length FDA in the second direction (geometric axis Y direction). A length of the second unfolded area Petition 870250088599, dated 09 / 30 / 2025, pages 85 / 96 44 / 44 folding NFA2 in the second direction (Y-axis geometric direction) can be greater than the length of the folding area FDA in the second direction (Y-axis geometric direction). [000189] A first display area DA1 can be placed in front of the display device 10. The first display area DA1 can overlap the folding area FDA, the first non-folding area NFA1, and the second non-folding area NFA2. Therefore, when the display device 10 is unfolded, an image can be displayed forward on the folding area FDA, the first non-folding area NFA1, and the second non-folding area NFA2 of the display device 10. [000190] A second DA2 display area can be arranged on the rear of the display device 10. The second DA2 display area can overlap the second non-folding NFA2 area. Therefore, when the display device 10 is folded, an image can be displayed forward on the second non-folding NFA2 area of ​​the display device 10. [000191] In Figures 14 and 15, a TH through hole in which an SDA camera is placed is arranged in the second non-folding area NFA2. However, the present invention is not limited to this. The TH through hole can also be arranged in the first non-folding area NFA1 or in the folding area FDA. [000192] In concluding the detailed description, those skilled in the art will observe that many variations and modifications can be made to the preferred embodiments without departing substantially from the principles of the present invention. Therefore, the described preferred embodiments of the invention are used in a generic and descriptive sense only and not for purposes of limitation. Petition 870250088599, dated 09 / 30 / 2025, pages 86 / 96

Claims

1 / 10 CLAIMS 1. Sweep driver (610), characterized in that it comprises stages that sequentially emit sweep signals to sweep signal lines (SCL) during an active period of an Nth frame, wherein N is a positive integer, and at least one of the stages comprises: an output node controller (SCC) that provides a gate activation voltage to a load node (Q) in response to a gate control signal (GCS) from a display driver (200); and an output controller (OUC) that emits a sweep clock signal, which is fed into a sweep clock terminal (SCI1, SCI2), to a connected sweep signal line (SCL) as a sweep signal when the gate activation voltage is supplied to the load node (Q), wherein the output node controller (SCC) comprises at least one thin-film transistor that includes an active first layer (ACT1), and is directly or indirectly connected to the load node (Q);and at least one other thin-film transistor that includes a second active layer (ACT2) in which a different oxide semiconductor material is used than the oxide semiconductor material of the first active layer (ACT1), and is directly connected to the charge node (Q).

2. Sweep driver (610), according to claim 1, characterized in that the output node controller (SCC) comprises: a first transistor (T1) activated when the load node (Q) is enabled by the gate activation voltage and providing either a sweep clock signal to a first capacitor (C1) connected to it in parallel; a second transistor (T2) activated when a load node (QB) is enabled by the gate activation voltage and providing a gate deactivation voltage to the first transistor (T1); a third transistor (T3) activated when the load node (Q) is enabled by the gate activation voltage and providing another sweep clock signal to the discharge node (QB);a fourth transistor (T4) activated in response to a line selection signal from a detection signal terminal (RSI) or a previous charging signal and providing the gate activation voltage to the charging node (Q); a fifth transistor (T5) activated in response to another clock sweep signal and providing the gate activation voltage to the discharging node (QB); a sixth transistor (T6) that electrically connects the charging node (Q) to another transistor or the first capacitor (C1) in response to either clock sweep signal; and a seventh transistor (T7) activated when the discharging node (QB) is enabled and that electrically connects the sixth transistor (T6) to the first capacitor (C1) and the first transistor (T1).

3. Sweep driver (610), according to claim 2, characterized in that the output controller (OUC) comprises: a load transistor (DT) activated by the gate activation voltage of the load node (Q) and which emits any sweep clock signal, which is fed into the sweep clock terminal (SCI1, SCI2), to a sweep output terminal (SCO) and the sweep signal line (SCL); and a discharge transistor (VT) activated by the gate activation voltage of the discharge node (QB) and which emits the gate deactivation voltage to the sweep output terminal (SCO) and the sweep signal line (SCL). Petition 870250088599, dated 09 / 30 / 2025, p. 34 / 96 3 / 10 4. Sweep driver (610), according to claim 3, characterized in that the discharge transistor (VT) comprises the first active layer (ACT1) comprising an oxide semiconductor, and in that the discharge transistor (VT) comprises the second active layer (ACT2) comprising another oxide semiconductor different from the first active layer (ACT1).

5. Sweep driver (610), according to claim 2, characterized in that the output node controller (SCC) further comprises an eighth transistor (T8) that disables the load node (Q) using the gate turn-off voltage or any sweep clock signal in response to the next load signal from a next stage.

6. Sweep driver (610), according to claim 5, characterized in that at least one of the second and fifth to seventh transistors (T2, T5, T6, T7) indirectly connected to the load node (Q) among the first to eighth transistors (T1-T8) included in the output node controller (SCC) comprises the first active layer (ACT1) comprising an oxide semiconductor, and at least one of the first, third, fourth and eighth transistors (T1, T3, T4, T8) directly connected to the load node (Q) among the first to eighth transistors (T1-T8) included in the output node controller (SCC) comprises the second active layer (ACT2) comprising an oxide semiconductor different from the oxide semiconductor of the first active layer (ACT1).

7. Sweep driver (610), according to claim 2, characterized in that the first transistor (T1) has a gate electrode connected to the load node (Q), a first electrode connected to a second sweep clock terminal (SCI2) and a second electrode connected to a previous load terminal and Petition 870250088599, dated 09 / 30 / 2025, page 35 / 96 4 / 10 a first electrode of the second transistor (T2), the second transistor (T2) has a gate electrode connected to the discharge node (QB), the first electrode connected to the second electrode of the first transistor (T1) and the previous load terminal and a second electrode connected to a gate turn-off voltage supply terminal, the third transistor (T3) has a gate electrode connected to the load node (Q), a first electrode connected to a first sweep clock terminal (SCI1) and a second electrode connected to the discharge node (QB),The fourth transistor (T4) has a gate electrode connected to the sensing signal terminal (RSI) or the previous charging terminal, a first electrode connected to a gate activation voltage supply terminal, and a second electrode connected to the charging node (Q). The fifth transistor (T5) has a gate electrode connected to the first clock sweep terminal (SCI1), a first electrode connected to the gate activation voltage supply terminal, and a second electrode connected to the discharging node (QB). The sixth transistor (T6) has a gate electrode connected to the second clock sweep terminal (SCI2), a first electrode connected to the charging node (Q), and a second electrode connected to the second electrode of the first transistor (T1) or a first electrode of the seventh transistor (T7). The seventh transistor (T7) has a gate electrode connected to the discharging node (QB).The first electrode is connected to the second electrode of the sixth transistor (T6), and a second electrode is connected to the second electrode of the first transistor (T1) and to the first capacitor (C1).

8. Sweep driver (610), according to claim 7, characterized in that the output controller (OUC) comprises: a load transistor (DT) having a first electrode connected to the second sweep clock terminal (SCI2), a gate electrode connected to the load node (Q) and a second electrode connected to the sweep output terminal (SCO); and a discharge transistor (VT) having a first electrode connected to the sweep output terminal (SCO), a gate electrode connected to the discharge node (QB) and a second electrode connected to a gate turn-off voltage supply terminal.

9. Sweep driver (610), according to claim 8, characterized in that the discharge transistor (VT) comprises the first active layer (ACT1) comprising an oxide semiconductor and the charge transistor (DT) comprises the second active layer (ACT2) comprising an oxide semiconductor different from the oxide semiconductor of the first active layer (ACT1).

10. Sweep driver (610), according to claim 7, characterized in that the output node controller (SCC) further comprises an eighth transistor (T8) having a gate electrode connected to a nearby load terminal, a first electrode connected to the previous load terminal or to the gate turn-off voltage supply terminal and a second electrode connected to the load node (Q).

11. Sweep driver (610), according to claim 10, characterized in that at least one of the second and fifth to seventh transistors (T2, T5, T6, T7) indirectly connected to the load node (Q) among the first to eighth transistors (T1-T8) included in the output node controller (SCC) comprises a first active layer (ACT1) comprising an oxide semiconductor, and at least one of the first, third, fourth and eighth transistors (T1, T3, T4, T8) directly connected to the load node (Q) among the first to eighth transistors (T1-T8) included in the output node controller (SCC) comprises the second active layer (ACT2) comprising an oxide semiconductor different from the oxide semiconductor of the first active layer (ACT1).

12. Scanning driver (610), according to claim 7, characterized in that the first active layer (ACT1) comprises indium, gallium and zinc oxide and the second active layer (ACT2) comprises indium, gallium, zinc and tin oxide.

13. Display device (10), characterized in that it comprises: a plurality of pixels (PX) arranged in a display area of ​​a display panel (100); a touch detection unit (TSU) mounted on the front of the display panel (100) and integrally formed with the display panel (100); a touch driver (400) that detects a touch using a plurality of touch electrodes arranged in the touch detection unit (TSU); a display driver (200) that controls data voltages supplied to the pixels (PX) and image display timing of the pixels (PX);and a scan driver (610) that sequentially drives scan signal lines (SCL), which are connected to pixels (PX), in response to a gate control signal (GCS) from the display driver (200), wherein the scan driver (610) comprises stages that sequentially output scan signals to the scan signal lines (SCL) during an active period of an Nth frame, wherein N is a positive integer, and at least one of the stages comprises: an output node controller (SCC) that provides a gate activation voltage to a load node (Q) in response to a gate control signal (GCS) from a display driver (200);and Petition 870250088599, dated 09 / 30 / 2025, page 38 / 96 7 / 10 an output control unit (OUC) that emits a sweep clock signal, which is fed into a sweep clock terminal (SCI1, SCI2), to a sweep signal line (SCL) connected as a sweep signal when gate activation voltage is supplied to the load node (Q), wherein the output node control unit (SCO) comprises at least one thin-film transistor comprising a first active layer (ACT1) and is indirectly connected to the load node (Q); and at least one other thin-film transistor comprising a second active layer (ACT2) comprising a semiconductor oxide material different from the first active layer (ACT1), and is indirectly connected to the load node (Q).; 14. Display device (10), according to claim 13, characterized in that the output node controller (SCC) comprises: a first transistor (T1) activated when the load node (Q) is enabled by the gate activation voltage and providing either a sweep clock signal to a first capacitor (C1) connected to it in parallel; a second transistor (T2) activated when a discharge node (QB) is enabled by the gate activation voltage and providing a gate deactivation voltage to the first transistor (T1); a third transistor (T3) activated when the load node (Q) is enabled by the gate activation voltage and providing another sweep clock signal to the discharge node (QB); a fourth transistor (T4) activated in response to a line selection signal from a sensing signal terminal (RSI) or a previous load signal and providing the gate activation voltage to the load node (Q);a fifth transistor (T5) activated in response to another sweep clock signal and providing gate activation voltage to the discharge node (QB); a sixth transistor (T6) that electrically connects the load node (Q) to another transistor or the first capacitor (01) in response to either a sweep clock signal; and a seventh transistor (T7) activated when the discharge node (QB) is enabled and that electrically connects the sixth transistor (T6) to the first capacitor (C1) and the first transistor (T1).

15. Display device (10), according to claim 14, characterized in that the output controller (OUC) comprises: a load transistor (DT) activated by the gate activation voltage of the load node (Q) and which emits any sweep clock signal, which is fed into the sweep clock terminal (SCI1, SCI2), to a sweep output terminal (SCO) and the sweep signal line (SCL); and a discharge transistor (VT) activated by the gate activation voltage of the discharge node (QB) and which emits the gate deactivation voltage to the sweep output terminal (SCO) and the sweep signal line (SCL).

16. Display device (10), according to claim 14, characterized in that the output node controller (SCC) further comprises an eighth transistor (T8) that disables the load node (Q) using the gate turn-off voltage or any sweep clock signal in response to the next load signal from a next stage.

17. Display device (10), according to claim 14, characterized in that the first transistor (T1) has a gate electrode connected to the load node (Q), a first electrode connected to a second sweep clock terminal (SCI2) and a second electrode connected to a previous charging terminal and a first electrode of the second transistor (T2), the second transistor (T2) has a gate electrode connected to the discharge node (QB), the first electrode connected to the second electrode of the first transistor (T1) and the previous charging terminal and a second electrode connected to a gate turn-off voltage supply terminal, the third transistor (T3) has a gate electrode connected to the load node (Q), a first electrode connected to a first sweep clock terminal (SCI1) and a second electrode connected to the discharge node (QB),The fourth transistor (T4) has a gate electrode connected to the sensing signal terminal (RSI) or the previous charging terminal, a first electrode connected to a gate activation voltage supply terminal, and a second electrode connected to the charging node (Q). The fifth transistor (T5) has a gate electrode connected to the first clock sweep terminal (SCI1), a first electrode connected to the gate activation voltage supply terminal, and a second electrode connected to the discharging node (QB). The sixth transistor (T6) has a gate electrode connected to the second clock sweep terminal (SCI2), a first electrode connected to the charging node (Q), and a second electrode connected to the second electrode of the first transistor (T1) or a first electrode of the seventh transistor (T7). The seventh transistor (T7) has a gate electrode connected to the discharging node (QB).The first electrode is connected to the second electrode of the sixth transistor (T6), and a second electrode is connected to the second electrode of the first transistor (T1) and to the first capacitor (C1).

18. Display device (10), according to claim 17, characterized in that the output controller (OUC) comprises: a load transistor (DT) having a first electrode connected to the second sweep clock terminal (SCI2), a gate electrode connected to the load node (Q) and a second electrode connected to the sweep output terminal (SCO); and a discharge transistor (VT) having a first electrode connected to the sweep output terminal (SCO), a gate electrode connected to the discharge node (QB) and a second electrode connected to a gate turn-off voltage supply terminal.

19. Display device (10), according to claim 17, characterized in that the output node controller (SCC) further comprises an eighth transistor (T8) having a gate electrode connected to a nearby load terminal, a first electrode connected to the previous load terminal or to the gate disable voltage supply terminal and a second electrode connected to the load node (Q).

20. Display device (10), according to claim 19, characterized in that at least one of the second and fifth to seventh transistors (T2, T5, T6, T7) indirectly connected to the load node (Q) among the first to eighth transistors (T1-T8) included in the output node controller (SCC) comprises a first active layer (ACT1) comprising an oxide semiconductor, and at least one of the first, third, fourth and eighth transistors (T1, T3, T4, T8) directly connected to the load node (Q) among the first to eighth transistors (T1-T8) included in the output node controller (SCC) comprises the second active layer (ACT2) comprising an oxide semiconductor different from the oxide semiconductor of the first active layer (ACT1). Petition 870250088599, dated 09 / 30 / 2025, p. 42 / 96

Images