Semiconductor chip, and method for manufacturing a semiconductor chip

Description

1 / 69 “ANTENNA MODULE AS A RADIO FREQUENCY (RF) INTEGRATED CIRCUIT (IC) CHIP WITH AN INTEGRATED ANTENNA SUBSTRATE AND RELATED MANUFACTURING METHODS REQUEST FOR PRIORITY

[0001] The present application claims priority to U.S. patent application serial number 18 / 300,067, filed April 13, 2023, entitled ANTENNA MODULE AS A RADIOFREQUENCY (RF) INTEGRATED CIRCUIT (IC) DIE WITH AN INTEGRATED ANTENNA SUBSTRATE, AND RELATED FABRICATION METHODS, which is incorporated herein by reference in its entirety. BACKGROUND I. Field of dissemination

[0002] The disclosure field refers to antenna modules, such as antenna-in-packages (AiP(s)), which include a radio-frequency (RF) integrated circuit (RFIC) coupled to an antenna(s) as part of an IC package. II. Background

[0003] Modern smartphones and other portable devices have expanded the use of different wireless links with a variety of technologies in different radio frequency bands. For example, fifth-generation (5G) cellular networks, commonly referred to as New Radio (NR) 5G, include frequencies in the 24.25 to 86 gigahertz (GHz) range, with the lower 19.25 GHz range (24.25 to 43.5 GHz) being the most likely to be used for mobile devices. This 5G communications frequency spectrum is in the millimeter wave (mmWave) range or millimeter band. mmWave Petition 870250089186, dated 10 / 01 / 2025, pp. 78 / 180 2 / 69 enables higher data rates than at lower frequencies, such as those used for Wi-Fi and current cellular networks. It may also be desirable to provide communication devices that support higher communication frequencies that are sub-mmWave to a sixth-generation (6G) frequency spectrum, such as the D-band frequency spectrum in the 110 GHz to 170 GHz frequency range, to utilize additional available frequency spectrum.

[0004] Radio frequency (RF) transceivers are incorporated into mobile devices and other portable devices that are designed to support communication signals in the desired frequency spectrum. To support the integration of an RF transceiver into a device, the RF transceiver can be integrated into an RF integrated circuit (IC) on an RF IC chip that is provided as part of an antenna module. The RF IC chip is implemented on an RF IC semiconductor wafer (RF IC chip). An antenna module may also be called an antenna-in-package (AiP). A conventional antenna module includes a wafer module that includes one or more RF ICs, a power management IC (PMIC). - power management IC) and passive electrical components (e.g., inductors, capacitors, etc.) mounted on a package substrate as a support structure. The RF IC chip includes an RF signal transmitter and receiver capable of modulating RF signals to be transmitted in supported frequency band(s) and demodulating received RF signals in supported frequency band(s). The package substrate includes a plurality of layers of Petition 870250089186, dated 10 / 01 / 2025, p. 79 / 180 3 / 69 Metallization (e.g., laminated FR2 metallization layers) includes metal lines / tracks for metal interconnects to provide chip-to-chip and external signal interfaces to the wafer module. The package substrate also includes other metallization layers in which one or more antennas are formed and are electrically coupled to the wafer module through the metal interconnects of the package substrate to be able to receive and radiate electrical RF signals as electromagnetic (EM) signals. The package substrate may include a plurality of antennas, also called an antenna array, to provide signal coverage over a larger intended area around the antenna module.

[0005] As the frequency spectrum supported by antenna modules increases, there is a need to design antennas in these antenna modules to be able to support higher frequencies, such as D-band frequencies, for example. SUMMARY OF THE DISCLOSURE

[0006] Aspects disclosed in the present invention include an antenna module as a radio frequency (RF) integrated circuit (IC) semiconductor wafer (wafer) with an integrated antenna substrate. The wafer with the integrated antenna substrate can be provided as part of a single IC chip that is manufactured as part of a wafer-level manufacturing process, for example. These related manufacturing processes are also disclosed. The chip includes an RF IC that includes an RF circuit (e.g., a front-end RF circuit). Petition 870250089186, dated 10 / 01 / 2025, p. 80 / 180 4 / 69 which includes RF signal transmission and / or reception capability. The RF IC is coupled to antenna elements on the antenna substrate as part of the chip to receive and radiate these RF signals. It may be desired that an antenna module support higher frequency communications that support shorter wavelengths (e.g., D-band frequencies). This may require smaller antenna elements that necessitate manufacturing processes that can form metal elements (e.g., metal traces, metal lines) in smaller line-space (L / S) metal patterns with metal interconnects in smaller pitches than may be possible in a package antenna (AiP), for example. In an AiP, the antenna layers are formed on a separate package substrate that is separately fabricated and packaged with an IC wafer via solder-coupled overhang structures as part of an IC package. In this sense, by way of example, to be able to form smaller antenna elements on an antenna substrate that supports higher frequencies with smaller L / S metal patterns and / or smaller pitch metal interconnects coupled to the antenna elements, the antenna elements are formed in one or more antenna layers as part of an antenna substrate that is formed on a semiconductor wafer (e.g., a complementary metal-oxide semiconductor (CMOS) wafer). The RF IC is formed on a semiconductor wafer as part of a wafer.In this way, the antenna layers can be formed as part of a wafer-level manufacturing process used to form the RF IC on the semiconductor wafer and to form the antenna layers on the same wafer. Petition 870250089186, dated 10 / 01 / 2025, page 81 / 180 5 / 69 smaller L / S metal patterns and / or smaller pitch metal interconnects to support antenna elements capable of supporting higher frequency communications. Furthermore, with the provision of an antenna module that integrates the antenna substrate into a wafer, the antenna module can be fully tested at the wafer level, if desired, to improve quality and performance.

[0007] In an illustrative aspect, the antenna substrate layers can be formed on the back side of the RF IC adjacent to (i.e., directly adjacent to or not directly (i.e., indirectly) adjacent to) a back side of a semiconductor layer of the RF IC in which the active semiconductor devices are formed. In one example, the back side of the semiconductor layer is on the opposite side of a front side of the semiconductor layer that is adjacent to a BEOL metallization structure. The semiconductor layer can be formed as part of a front-end-of-line (FEOL) process. Forming the antenna substrate on the back side of the RF IC and adjacent to the back side of the semiconductor layer can locate the antenna elements of the antenna substrate closer to the metal layers of the IC to minimize the distance between them, reducing transmission losses as a result.For example, the antenna substrate can be formed adjacent to a layer of bulk semiconductor material (e.g., bulk silicon substrate) if the RF IC is a bulk device. Alternatively, as another example, the antenna substrate can be formed adjacent to a buried oxide layer (BOX - buried oxide) if the RF IC is a semiconductor-on-insulator (SOI - semiconductor-on) device. Petition 870250089186, dated 10 / 01 / 2025, p. 82 / 180 6 / 69 insulator). In these examples, the metal layers formed as part of a back-end-of-line (BEOL) interconnect structure of the RF IC to provide signal routing to the RF IC are formed on the opposite side of the semiconductor layer adjacent to the antenna substrate. In this example, the formation of the antenna substrate layers on the back side of the RF IC allows the antenna layers to be stacked on a loop coupled to the semiconductor layer that will not interfere with the formation of the RF IC's BEOL interconnect structure.

[0008] Furthermore, through the antenna module that is provided as a wafer that includes the integrated antenna substrate, the distance between the antenna layers, in which the antenna elements are formed, and the RF IC is reduced compared to the distance between antenna layers and a wafer in an AiP. This reduces the clearance distance between the antenna elements and the RF IC, which, in turn, reduces transmission losses. It can be particularly important to reduce transmission losses in the antenna module that supports higher frequencies (e.g., D-band frequencies), as data transmission rates can be higher, thus making it more difficult to keep the signal-to-noise ratio (SNR) of RF signals below desired limits.The reduced clearance distance between the antenna elements and the RF IC on the chip can also reduce the distance between the antenna elements and a ground plane formed in metal layers of the RF IC (e.g., in the BEOL interconnect structure) to further reduce transmission losses. Petition 870250089186, dated 10 / 01 / 2025, page 83 / 180 7 / 69

[0009] In other exemplary aspects, a dielectric material substrate can be formed adjacent to the RF IC semiconductor layer to provide a surface onto which the antenna layers of the antenna substrate can be built as part of a wafer-level fabrication process for the wafer. In this example, because the wafer is fabricated using a wafer-level fabrication process, the dielectric material substrate can be formed as a silicon substrate. The dielectric material substrate can serve as a handle to form the semiconductor layer and the BEOL interconnect structure of the RF IC. The antenna layers of the antenna substrate can then be built onto the dielectric material substrate on an opposite side of the semiconductor layer.The dielectric substrate can be processed (e.g., milled) to control the desired clearance distance between the antenna elements formed in the antenna layers of the antenna substrate and the RF IC in the semiconductor layer to control transmission loss. Vias (e.g., through-silicon vias (TSVs)) can be formed in the antenna substrate and through the semiconductor layer and the BEOL interconnect structure of the RF IC to interconnect the antenna elements to the RF IC. The wafer fabrication process for the RF IC wafer can support control of the dielectric substrate thickness between the antenna substrate and the RF IC that is compatible with the height limits of the via formation process.

[0010] In still other exemplary aspects, the dielectric material substrate (for example, a substrate Petition 870250089186, dated 10 / 01 / 2025, page 84 / 180 The 8 / 69 silicon chip between the antenna substrate and the RF IC may have a higher permittivity than desired, thus resulting in undesirable transmission losses. These transmission losses may be unacceptable, especially if the antenna module and its antenna elements are designed to support higher frequency communications. In this sense, as an example, the dielectric material substrate between the antenna substrate and the RF IC of the chip can be provided as a porous silicon layer. In this sense, as an example, after the semiconductor layer and the BEOL interconnect structure of the RF IC are formed on the dielectric material substrate in the form of a silicon layer as a handle layer, a porosification process can be performed on the silicon layer to control and tune its permittivity and tangent loss to the desired levels to achieve the desired performance for the supported communication frequencies.Controlling the porosification of the silicon layer between the semiconductor layer and the antenna substrate can control the permittivity of the silicon layer and thus control transmission losses between the antenna elements on the antenna substrate and the RF IC. In another example, to avoid damaging the semiconductor layer when performing the porosification process on the silicon layer adjacent to the semiconductor layer, a stripping stop layer (e.g., a nitride layer) can be placed on the silicon layer as a handle layer before forming the semiconductor layer on the handle silicon layer. The stripping stop layer prevents porosification of the layer. Petition 870250089186, dated 10 / 01 / 2025, p. 85 / 180 9 / 69 semiconductor when the silicon layer is processed into a porous silicon layer.

[0011] In another illustrative aspect, in an antenna module provided as a wafer that includes the integrated antenna substrate, the antenna layers of the antenna substrate can be formed as redistribution layers (RDLs). RDLs can be constructed on a semiconductor wafer as part of an RDL fabrication process of a wafer-level fabrication process. RDL fabrication processes support the formation of smaller L / S metal patterns and smaller pitch metal interconnects. RDLs can also support the redistribution of connections to the antenna elements, so that these connections do not have to be aligned to metal interconnects (e.g., vias) coupling the antenna elements through the antenna substrate to the RF IC.

[0012] In this sense, in an exemplary aspect, a semiconductor wafer is provided. The semiconductor wafer comprises a semiconductor layer and a BEOL interconnect structure. The semiconductor layer comprises a first side, a back side opposite the first side, and a radio frequency (RF) circuit. The BEOL interconnect structure is coupled to the RF circuit. The BEOL interconnect structure comprises a front side and a second side opposite the front side, the second side coupled to the first side of the semiconductor layer. The semiconductor wafer also comprises an antenna substrate adjacent to the back side of the semiconductor layer. The antenna substrate comprises one or more Petition 870250089186, dated 10 / 01 / 2025, p. 86 / 180 10 / 69 antenna layers, a first antenna layer of one or more antenna layers comprising one or more antenna elements. The semiconductor chip also comprises one or more first paths, each coupling one antenna element of the one or more antenna elements to the BEOL interconnect structure to couple the one or more antenna elements to the RF circuit.

[0013] In another exemplary aspect, a method for manufacturing a semiconductor wafer is provided. The method for manufacturing the wafer comprises forming a semiconductor layer comprising a first side, a back side opposite the first side, and a radio frequency (RF) circuit. The method for manufacturing the wafer also comprises forming a BEOL interconnect structure coupled to the RF circuit, wherein the BEOL interconnect structure comprises a front side and a second side opposite the front side, the second side coupled to the semiconductor layer.The method for manufacturing the wafer also comprises forming an antenna substrate adjacent to the back side of the semiconductor layer, which comprises forming one or more antenna layers, wherein a first antenna layer of the one or more antenna layers comprises one or more antenna elements and forms one or more first paths, each coupling one antenna element of the one or more antenna elements to the BEOL interconnect structure to couple the one or more antenna elements to the RF circuit. BRIEF DESCRIPTION OF THE FIGURES

[0014] Figures 1A and 1B are side views of an antenna module in the form of a package antenna (AiP) that includes an integrated circuit (IC) chip. Petition 870250089186, dated 10 / 01 / 2025, page 87 / 180 11 / 69 radio frequency (RF) coupled to a package substrate that supports antennas formed in layers of metallization on it;

[0015] Figures 2A and 2B are side views of an exemplary semiconductor wafer (wafer) providing an antenna module, wherein the wafer includes an RF IC with an RF circuit and an integrated antenna substrate to provide an antenna for the RF circuit, wherein the antenna substrate is adjacent to the rear side of the RF IC;

[0016] Figure 3 is a side view of an exemplary electronic device that includes the semiconductor wafer in Figures 2A and 2B coupled to a package substrate, which, in turn, is coupled to a circuit board;

[0017] Figure 4 is a side view of another exemplary wafer providing an antenna module, wherein the wafer is a semiconductor-on-insulator (SOI) device with an RF circuit and an integrated antenna substrate to provide an antenna for the RF circuit, wherein the wafer additionally includes a layer of dielectric material in the form of a porous silicon substrate disposed between a semiconductor layer of the RF IC and the antenna substrate to support the formation of the antenna substrate and to control the clearance distance between the antenna elements and the RF circuit to control transmission losses;

[0018] Figure 5 is a side view of another exemplary wafer providing an antenna module, wherein the wafer includes a bulk device with an RF circuit and an integrated antenna substrate to provide an antenna for the RF circuit, wherein the wafer additionally includes a layer of dielectric material arranged Petition 870250089186, dated 10 / 01 / 2025, pp. 88 / 180 12 / 69 between a semiconductor layer of the RF IC and the antenna substrate to support the formation of the antenna substrate and to control the clearance distance between the antenna elements and the RF circuit to control transmission losses;

[0019] Figure 6 is a flowchart illustrating an exemplary manufacturing process for manufacturing a wafer that provides an antenna module, wherein the wafer includes an RF IC with an RF circuit and an integrated antenna substrate to provide an antenna for the RF circuit, wherein the antenna substrate is adjacent to the rear side of the RF IC, including, but not limited to, the wafers in Figures 2A to 5;

[0020] Figures 7A to 7E are a flowchart illustrating another exemplary fabrication process for fabricating a wafer that provides an antenna module, wherein the wafer is a SOI device with an RF circuit and an integrated antenna substrate to provide an antenna for the RF circuit, wherein the wafer additionally includes a layer of dielectric material disposed between a semiconductor layer of the RF IC and the antenna substrate to support the formation of the antenna substrate and to control the clearance distance between the antenna elements and the RF circuit to control transmission losses, including those, but not limited to, wafers in Figures 2A to 5;

[0021] Figures 8A to 8F illustrate exemplary manufacturing stages during the manufacture of the wafer produced according to the manufacturing process in Figures 7A to 7E; Petition 870250089186, dated 10 / 01 / 2025, pp. 89 / 180 13 / 69

[0022] Figures 9A to 9E are a flowchart illustrating another exemplary manufacturing process for fabricating a wafer that provides an antenna module, wherein the wafer includes a bulk device with an RF circuit and an integrated antenna substrate to provide an antenna for the RF circuit, wherein the wafer additionally includes a layer of dielectric material disposed between a semiconductor layer of the RF IC and the antenna substrate to support the formation of the antenna substrate and to control the clearance distance between the antenna elements and the RF circuit to control transmission losses, including those, but not limited to, wafers in Figures 2A to 5;

[0023] Figures 10A to 10F illustrate exemplary manufacturing stages during the manufacturing of the wafer according to the manufacturing process in Figures 9A to 9E;

[0024] Figure 11 is a block diagram of an exemplary wireless communication device comprising a chip providing an antenna module, wherein the chip includes an RF IC with an RF circuit and an integrated antenna substrate to provide an antenna for the RF circuit, wherein the antenna substrate is adjacent to the rear side of the RF IC, including, but not limited to, the chips in Figures 2A to 5, 8F and 10F, and which may be manufactured according to any of the exemplary manufacturing processes in Figures 6, 7A to 7E and 9A to 9E;

[0025] Figure 12 is a block diagram of an exemplary processor-based system that includes a chip providing an antenna module, wherein the chip includes an RF IC with an RF circuit and a substrate. Petition 870250089186, dated 10 / 01 / 2025, pp. 90 / 180 14 / 69 integrated antenna to provide an antenna for the RF circuit, wherein the antenna substrate is adjacent to the rear side of the RF IC, including, but not limited to, the chips in Figures 2A to 5, 8F and 10F, and which may be manufactured according to any of the exemplary manufacturing processes in Figures 6, 7A to 7E and 9A to 9E. DETAILED DESCRIPTION

[0026] With reference now to the figures in the drawings, several exemplary aspects of the present disclosure are described. The word exemplary is used in the present invention to mean serving as an example, an instance or an illustration. Any aspect described in the present invention as exemplary should not necessarily be interpreted as preferential or advantageous in relation to other aspects.

[0027] Aspects disclosed in the present invention include an antenna module as a radio frequency (RF) integrated circuit (IC) semiconductor wafer (wafer) with an integrated antenna substrate. The wafer with the integrated antenna substrate can be provided as part of a single IC chip that is manufactured as part of a wafer-level manufacturing process, for example. These related manufacturing processes are also disclosed. The chip includes an RF IC that includes an RF circuit (e.g., a front-end RF circuit) that includes RF signal transmission and / or reception capability. The RF IC is coupled to antenna elements on the antenna substrate as part of the chip to receive and radiate these RF signals. It may be desired that an antenna module support higher frequency communications that support Petition 870250089186, dated 10 / 01 / 2025, page 91 / 180 15 / 69 shorter wavelengths (e.g., D-band frequencies). This may require smaller antenna elements which necessitate manufacturing processes that can form metal elements (e.g., metal traces, metal lines) in smaller line-space (L / S) metal patterns with metal interconnects in smaller pitches than might be possible in a package antenna (AiP), for example. In an AiP, the antenna layers are formed on a separate package substrate that is separately fabricated and packaged with a wafer through solder-coupled overhang structures as part of an IC package.In this sense, by way of example, in order to form smaller antenna elements on an antenna substrate that supports higher frequencies with smaller L / S metal patterns and / or smaller pitch metal interconnects coupled to the antenna elements, the antenna elements are formed in one or more antenna layers as part of an antenna substrate that is formed on a semiconductor wafer (e.g., a complementary metal-oxide semiconductor (CMOS) wafer). The RF IC is formed on a semiconductor wafer as part of a wafer. In this way, the antenna layers can be formed as part of a wafer-level manufacturing process used to form the RF IC on the semiconductor wafer and to form the antenna layers on the same wafer with smaller L / S metal patterns and / or smaller pitch metal interconnects to support antenna elements capable of supporting higher frequency communications.Furthermore, with the provision of an antenna module that integrates the antenna substrate into a single wafer, the antenna module can be... Petition 870250089186, dated 10 / 01 / 2025, page 92 / 180 16 / 69 fully tested at the wafer level, if desired, to improve quality and yield.

[0028] Before discussing examples of a wafer that provides an antenna module, wherein the wafer includes an RF IC with an RF circuit and an integrated antenna substrate to provide an antenna for the RF circuit starting in Figure 2A, an example of an antenna module 100 that is provided in the form of an AiP as a package-on-package (PoP) structure is first discussed with reference to Figures 1A and 1B below.

[0029] In this sense, Figure 1A is a side view of antenna module 100 which is an IC package that is configured in a side-by-side arrangement. Figure 1B is also a partial side view of antenna module 100 in Figure 1A, but rotated one hundred and eighty (180) degrees in the vertical direction (Z-axis direction) to further illustrate antenna module 100. Antenna module 100 includes an antenna substrate 102 that supports antenna elements (e.g., patch and / or dipole antenna elements) to support RF communications. Antenna module 100 includes an IC wafer layer 106 arranged in a horizontal plane (X-axis and Y-axis direction plane), wherein the IC wafer layer 106 includes an RF semiconductor IC wafer (RF IC wafer) 108 that includes an RF transceiver. The RF IC 108 wafer may be in the form of an encapsulated IC chip 109.The IC 106 wafer layer with the RF IC 108 wafer is mounted on a package 110 substrate to provide a support structure for the IC 106 wafer layer and also to provide an interconnect structure for attaching the RF IC wafer. Petition 870250089186, dated 10 / 01 / 2025, page 93 / 180 17 / 69 108 to other components and circuits in the antenna module 100. The antenna module 100 could also include a separate adjacent power management IC (PMIC) wafer 112 (which could also be an IC chip), as shown in Figure 1A, which provides a power source for the RF IC wafer 108. The RF IC wafer 108 and the PMIC wafer 112 are arranged side-by-side in a horizontal direction (X-axis direction). The IC wafer layer 106 also includes other passive components 114 (e.g., capacitors, inductors) that are electrically coupled through the package substrate 110 to the RF IC wafer 108 and / or the PMIC wafer 112 as part of the circuits formed therein. The size of these passive components 114 may be such that it is not desirable or feasible to integrate them into the RF IC 108 chip or the PMIC 112 chip.An electromagnetic interference (EMI) shield 117 is arranged around the RF chip IC 108 and other components in the chip layer IC 106.

[0030] Continuing with reference to Figure 1A, in this example, the package substrate 110 includes a metallization substrate 116 that is adjacent to the IC wafer layer 106. The metallization substrate 116 includes a plurality of substrate metallization layers 118, each of which includes metal interconnects 120 (e.g., pads, vertical interconnect accesses (vias), traces, lines) formed thereon to provide interconnect structures to facilitate interconnections to provide an electrical interface between the RF IC wafer 108 and other components and circuits in the antenna module 100. The interconnects of Petition 870250089186, dated 10 / 01 / 2025, page 94 / 180 18 / 69 wafer 121 couples the RF IC wafer 108 to the metal interconnects 120 on the metallization substrate 116. The metallization substrate 116 may be a coreless substrate. The metallization layers of substrate 118 could be formed as separate substrate layers that are laminated together to form the metallization substrate 116. In this example, the metallization substrate 116 is coupled to a core substrate 122 as part of the package substrate 110. The core substrate 122 also includes one or more metallization layers 124 that include metal interconnects 126 coupled to vias 128 (e.g., metal pillars) coupled to the metal interconnects 120 on the adjacent metallization substrate 116 to provide electrical connectivity between the metallization substrate 116 and the core substrate 122.

[0031] Still referring to Figures 1A and 1B, the packet substrate 110 in the antenna module 100 also includes the antenna substrate 102, which may be a pre-impregnation or a laminate substrate. The antenna substrate 102 is coupled to the core substrate 122, so that the core substrate 122 is disposed between the antenna substrate 102 and the metallization substrate 116 in the vertical direction (Z-axis direction), in this example. The antenna substrate 102 also includes one or more metallization layers 130 which include metal interconnects 132 coupled to vias 134 coupled to metal interconnects 126 on the core substrate 122. The antenna substrate 102 includes four (4) antennas 136(1) to 136(4) in this example, which include metal patches, which are electrically coupled to the RF chip IC 108 through interconnects between the antennas 136(1) to Petition 870250089186, dated 10 / 01 / 2025, page 95 / 180 19 / 69 136(4) and the metal interconnects 120, 126, 132 on the respective metallization substrate 116, on the core substrate 122 and on the antenna substrate 102. In this example, each antenna 136(1) to 136(4) is a patch antenna that includes antenna elements in the form of first antenna elements 138(1) to 138(4) in the form of metal patches adjacent to the core substrate 122 and second metal patches 140(1) to 140(4) arranged below the respective first antenna elements 138(1) to 138(4). The first antenna elements 138(1) to 138(4) are coupled to the RF chip IC 108 via the via 134 and metal interconnects. 132, 126, 120 which act as an antenna feed line. The second metal patches 140(1) to 140(4) are not in contact with the first antenna elements 138(1) to 138(4), but instead, the second metal patches 140(1) to 140(4) are configured to be electromagnetically (EM) coupled to the first antenna elements 138(1) to 138(4) when the first antenna elements 138(1) to 138(4) receive an RF signal to be radiated. Similarly, when the second metal patches 140(1) to 140(4) are energized by a received RF signal, the second metal patches 140(1) to 140(4) are EM coupled to the first antenna elements 138(1) to 138(4) with the received RF signal.

[0032] Antenna elements 138(1) to 138(4), 140(1) to 140(4) on antenna substrate 102 of antenna module 100 are sized to support the desired wavelengths of the desired antenna module 100 communication frequency capability. As an example, antenna elements 138(1) to 138(4), 140(1) to 140(4) can be patches Petition 870250089186, dated 10 / 01 / 2025, page 96 / 180 20 / 69 metal that are 3.0 millimeters (mm) by 3.0 mm to support the 5G communication frequency spectrum. The manufacturing processes available to manufacture an AiP such as antenna module 100 in Figure 1B may be sufficient to provide the metal interconnects 132 on the antenna substrate 102 to support an L / S and pitch metal pattern to support interconnection to antenna elements 138(1) to 138(4), 140(1) to 140(4) according to their shape and size. However, as an example, for higher communication frequencies, such as in the D-band frequency spectrum, the wavelength supported by antenna elements 138(1) to 138(4), 140(1) to 140(4) may be such that antenna elements 138(1) to 138(4), 140(1) to 140(4) need to be manufactured in layers of metallization of the antenna substrate 102 of a much smaller size (e.g. 150 micrometers (pm) by 150 pm). This is because the higher the frequency of a signal, the shorter its wavelength will be.The manufacturing techniques available for fabricating the antenna substrate. 102 may not be able to form the metal interconnects 132 on the antenna substrate 102 in a sufficiently small or thin L / S metal pattern and pitch to be able to interconnect to the smaller antenna elements. Thus, an antenna module such as antenna module 100 in Figures 1A and 1B, which is an AiP or PoP package, may not be able to be manufactured sufficiently to support higher frequency communications.

[0033] With reference to Figure 1B, the clearance shown as distance D1 between antenna elements 138(1) to 138(2) and RF chip IC 108 of antenna module 100 must also be compatible to provide compensation. Petition 870250089186, dated 10 / 01 / 2025, page 97 / 180 21 / 69 desired transmission loss versus antenna module form factor 100. Only antenna elements 138(1) to 138(2) and 140(1) to 140(2) for antennas 136(1) to 136(2) are shown in Figure 1B. As shown in Figure 1B, in this example, the RF chip IC 108 includes a power amplifier (PA) 142 and a low-noise amplifier (LNA). 144 formed in a semiconductor layer 146. The RF chip IC 108 also includes a line back-end interconnect structure (BEOL) 148 which includes a plurality of metal layers of insulated metal lines or tracks to provide interconnect paths in a vertical direction (Z-axis direction) between PA 142 and LNA 144, and the metallization substrate 116. These PA 142 and LNA 144 are exemplary circuits in the RF chip IC 108 that support the ability to receive and transmit RF signals with antennas 136(1) to 136(2). PA 142 and LNA 144 are located at a distance D1 from the antenna elements 138(1) to 138(2). As the frequency of a signal increases, the transmission losses also increase. Thus, it may be important to provide short interconnection paths between the RF chip IC 108 and the antenna elements 138(1) to 138(2) in the antenna module 100 to reduce transmission losses.In antenna module 100 in Figure 1B as an AiP, the clearance distance D1 can be between 500 and 600 pm based on the size of the antenna substrate 102, the core substrate 122, and the metallization substrate 116 according to their manufacturing techniques. Furthermore, if the clearance distance D1 is too large, there is a risk of increased EMI (and therefore a lower signal-to-noise ratio (SNR)) between the RF chip IC 108 and the antenna elements. Petition 870250089186, dated 10 / 01 / 2025, page 98 / 180 22 / 69 138(1) to 138(2) leading to reduced performance. The clearance distance Di also affects the distance between the antenna elements 138(1) to 138(2) and a ground plane that may be provided on the metallization substrate 116, for example. The clearance distance D1 also affects the clearance distance between the antenna elements 138(1) to 138(2) and any ground plane, because the clearance distance D1 affects the impedance, radiation pattern and gain of the antenna, which affect the data transfer rates.

[0034] This clearance distance Di between antenna elements 138(1) to 138(2) and RF chip IC 108 may be acceptable to provide the desired performance in antenna module 100 for mmWave frequencies, for example, but this clearance distance Di may result in unacceptable losses for higher frequencies (e.g., D-band frequencies). For example, the clearance distance Di between antenna elements 138(1) to 138(2) and RF chip IC 108 may ideally be 70 to 80 pm to avoid transmission losses between RF chip IC 108 and antenna elements 138(1) to 138(2) that would result in unacceptable performance based on the performance parameters affected by such clearance distance as discussed above.It may not be possible to manufacture antenna module 100 in Figures 1A and 1B with such a reduced clearance distance D1 between antenna elements 138(1) to 138(2) and RF chip IC 108 due to the PoP configuration and due to manufacturing process limitations for manufacturing antenna substrate 102, core substrate 122 and / or metallization substrate 116 of package substrate 110 of antenna module 100. Petition 870250089186, dated 10 / 01 / 2025, page 99 / 180 23 / 69

[0035] Thus, in conclusion, the 100 antenna module as an AiP in Figures 1A and 1B may not be feasible for supporting higher frequency RF signals, such as in the D-band frequency spectrum, for example. To support the transmission of higher frequency RF signals, the antenna elements may need to be manufactured in a smaller size to be compatible with (i.e., support) shorter wavelengths of higher frequency RF signals. This may require that an antenna substrate of an antenna module be manufactured with metal interconnects of a smaller L / S pattern and / or pitch that is capable of being manufactured on a 102 antenna substrate as in the 100 antenna module in Figures 1A and 1B according to package substrate manufacturing technologies.Antenna elements that are sized to support shorter wavelengths are smaller in size, so the metal interconnects on the antenna substrate 102 may not be able to be manufactured small enough to provide interconnections to the antenna elements without risk of short circuits. Furthermore, to support such higher frequency RF signals, the clearance distance D1 between antenna elements 138(1) to 138(2) and the RF chip IC 108 needs to be reduced to a smaller size than can be provided in antenna module 100 due to manufacturing process limitations to reduce signal path distance and EMI to achieve a desired SNR.

[0036] In this sense, to provide an antenna module that may be able to support higher RF signal frequencies (for example, D-band frequencies from 110 to 170 gigahertz (GHz)), the antenna module Petition 870250089186, dated 10 / 01 / 2025, pp. 100 / 180 24 / 69 can be formed as part of a wafer and not an AiP or a PoP like the 100 antenna module in Figures 1A and 1B. As described in more detail below, integrating the antenna module into a wafer can enable the metal interconnects in the antenna layer on the antenna substrate in the antenna module to be manufactured with a smaller L / S pattern and / or pitch to provide interconnects with smaller antenna elements formed there to support higher RF signal frequencies. Additionally, as described in more detail below, integrating the antenna module into a wafer can also enable the clearance distance between the antenna elements and the ICs coupled to the wafer, which are the circuits to support RF signal transmission and reception, to be reduced as a function of the manufacturing process techniques that can be employed to manufacture the wafer.The wafer can be manufactured using a wafer-level manufacturing process, which may allow antenna substrate layers to be stacked on a substrate within the wafer to minimize the height distance of the antenna layers and thus minimize the clearance distance between the antenna elements and the ICs coupled to the wafer. These possibilities may allow the antenna module integrated into the wafer to be manufactured in a way that is compatible with, and can support, higher RF signal frequencies that may not be possible in an AiP, such as the 100 antenna module in Figures 1A and 1B.

[0037] In this sense, Figures 2A and 2B are side views of an exemplary chip 200 that provides an integrated antenna module 202 integrated into the chip 200 that Petition 870250089186, dated 10 / 01 / 2025, pp. 101 / 180 25 / 69 is capable of supporting higher frequency RF signals (e.g., D-band frequencies). However, chip 200 in Figures 2A and 2B is not required to support RF signals of any particular frequency or frequency band. The 200 wafer is an RF wafer which is a semiconductor wafer which includes an RF IC 204 with RF circuits 206. The RF circuits 206 are electrically coupled to the antenna elements 208 on an integrated antenna substrate 210 provided in the 200 wafer to provide an antenna(s) 212 for the RF circuits 206. In this example, six (6) antenna elements 208(1) to 208(6) in the form of metal patch antennas that form patches in the horizontal directions (X-axis and Y-axis directions) form six (6) respective antennas 212(1) to 212(6), but this is not limiting.Thus, as discussed in more detail below, the 200 wafer with the integrated antenna substrate 210 can be provided as part of a single IC chip 209 that is manufactured as part of a wafer-level manufacturing process, for example. The 200 wafer includes the RF IC 204 which includes the RF circuits 206 (e.g., front-end RF circuits) to provide RF signal transmission and / or reception capability. In this example, for the antenna module 202 integrated into the 200 wafer with smaller L / S patterns and / or smaller pitch metal interconnects on the antenna substrate 210 to support interconnects with antenna elements that support higher RF signal frequencies, the antenna elements. 208(1) to 208(6) are formed on antenna substrate 210 on a semiconductor wafer (e.g., a complementary metal-oxide-semiconductor (CMOS) wafer). RF IC 204 is Petition 870250089186, dated 10 / 01 / 2025, page 102 / 180 26 / 69 formed on the semiconductor wafer as part of the 200 wafer. In this way, the antenna substrate 210 can be formed as part of a wafer-level manufacturing process used to form the RF IC 204 on the semiconductor wafer and to form the antenna substrate 210 with smaller L / S patterns and / or smaller pitch metal interconnects to support antenna elements capable of supporting higher frequency communications. Furthermore, with the provision of the antenna module 202 which integrates the antenna substrate 210 onto the 200 wafer, the antenna module 202 can be fully tested at the wafer level, if desired, to improve quality and performance.

[0038] With continued reference to Figure 2B, chip 200 in this example includes RF IC 204 which includes RF circuits 206. RF circuits 206 can be included as part of an LNA 214 and PA 216 (and / or, for example, other RF front-end circuits) to provide RF signal transmission and / or reception capability as an example. RF IC 204 includes a semiconductor layer 218 (e.g., a silicon layer) where active electrical devices (e.g., transistors) are formed (and therefore can also be called the active semiconductor layer). The semiconductor layer 218 has a first side 220 and a side 222 opposite the first side 220 in the vertical direction (Z-axis direction). The opposite side 222 of the semiconductor layer 218 is also called the back side 222, because it is the side of the semiconductor layer 218 that is not adjacent to the BEOL 224 interconnect structure, while the first side 220 is adjacent to the BEOL 224 interconnect structure.The back side 222 of the layer. Petition 870250089186, dated 10 / 01 / 2025, pp. 103 / 180 27 / 69 semiconductor 218, which is the back side 222 of RF IC 204 in this example, has a back side or rear surface in this example that is on the opposite side of the first side 220 adjacent to where RF circuits 206 are formed. The back side 222 of RF IC 204 may not contain active electronic components or electrical connections. Active components 225, such as transistors, can be formed in the semiconductor layer 218 as part of RF circuits 206 adjacent to the first side 220 of the semiconductor layer 218, which is adjacent to and can be coupled to the BEOL interconnect structure 224. In this example, the RF IC 204 is a semiconductor-on-insulator (SOI) device because the semiconductor layer 218 includes a semiconductor substrate 229 (e.g., silicon substrate) adjacent to the back side 222 of the semiconductor layer 218 and a buried oxide layer (BOX) 227 adjacent to the first side 220 of the semiconductor layer 218.The BOX 227 layer is located between the semiconductor substrate 229 and the first side 220 of the semiconductor layer 218. The BOX 227 layer creates an insulating layer buried between the semiconductor substrate 229 and the first side 220 of the semiconductor layer 218.

[0039] With continuous reference to Figure 2B, RF IC 204 also includes the BEOL 224 interconnect structure adjacent to the semiconductor layer 218. Typically, the BEOL 224 interconnect structure is formed in the semiconductor layer 218 as part of a BEOL fabrication process in a wafer fabrication process after the semiconductor substrate of the semiconductor layer 218 has been fabricated and the active components 225 have been formed in the layer. Petition 870250089186, dated 10 / 01 / 2025, pp. 104 / 180 28 / 69 semiconductor 218 as part of a line front-end fabrication process (FEOL). The BEOL 224 interconnect structure includes a plurality of metal layers 226(1) to 226(4) (also known as metallization layers 226(1) to 226(4)) that are adjacent to each other in a vertical direction (Z-axis direction) each including metal interconnects 228(1) to 228(4) formed as metal tracks or metal lines in a respective insulating layer 230(1) to 230(4). Secondary pathways 232(1) to 232(3) (e.g., through-silicon pathways (TSVs)) are formed in the respective metal layers 226(2) to 226(4) to interconnect the metal interconnections 228(1) to 228(4) in different metal layers 226(1) to 226(4) to form signal routing paths to RF IC 204 and between RF IC 204 and antenna substrate 210.The BEOL 224 interconnect structure has a front side 234 and a second side 236 opposite the front side 234 in the vertical direction (Z-axis direction). The second side 236 of the BEOL 224 interconnect structure is adjacent to and coupled to the semiconductor layer 218 and its RF circuit 206 in this example. Side 234 of the BEOL 224 interconnect structure is also called the front side 234 of RF IC 204, because it is the side of RF IC 204 that is adjacent to the external metal interconnects where the 200 pad is coupled to an external device as part of the BEOL 224 interconnect structure. The front side 234 of RF IC 204 and BEOL interconnect structure 224 is a side of RF IC 204 where the metal interconnects 228(1) of BEOL interconnect structure 224 are formed to provide connections to RF circuits 206. With reference to Figures 2A and 2B, the antenna substrate 210 is Petition 870250089186, dated 10 / 01 / 2025, pp. 105 / 180 29 / 69 provided on the 200 pad adjacent to the rear side 222 of RF IC 204. In this example, the antenna substrate 210 is not directly adjacent to the rear side 222 of RF IC 204, being disposed on the same side as the rear side 222 of RF IC 204 opposite the front side 234 of RF IC 204, because, as discussed below, a dielectric material substrate 250 is disposed between the antenna substrate 210 and the rear side 222 of RF IC 204 in the vertical direction (Z-axis direction). Not directly (or indirectly) adjacent means that an object (e.g., the antenna substrate 210) is not directly next to or in contact with another object (e.g., the rear side 222), but there is another intervening object between such objects. As an alternative option, the antenna substrate 210 may be directly adjacent to the rear side 222 of RF IC 204.Directly adjacent objects are objects that are directly next to each other or attached to each other without the presence of an intervening object between them.

[0040] In this example wafer 200 in Figures 2A and 2B, the antenna substrate 210 includes a plurality of antenna layers 238(1) to 238(3). The antenna layers 238(1) to 238(3) may be metal layers or metallization layers that are fabricated as or similar to the metal layers 226(1) to 226(4) in the BEOL interconnect structure 224. Metal interconnects 240(1) to 240(3) in the form of metal lines or tracks may be formed in the respective antenna layers 238(1) to 238(3). The metal interconnections 240(3) formed in the first antenna layer 238(3) in this example are the antenna elements 208(1) to 208(6) which each form the respective antennas 212(1) Petition 870250089186, dated 10 / 01 / 2025, pp. 106 / 180 30 / 69 to 212(6). For example, antenna elements 208(1) to 208(6) could be metal patch antennas. As an example, since the antenna substrate 210 can be fabricated as an integrated part of the wafer 200, the same wafer-level processing techniques used to fabricate the RF IC 204 can also be used to fabricate the antenna layers 238(1) to 238(3) of the antenna substrate 210. In this way, it may be feasible to fabricate the metal interconnects 240(1) to 240(3) (e.g., metal lines or metal traces) in the respective antenna layers 238(1) to 238(3) of a sufficiently smaller L / S metal pattern and / or pitch to form smaller antenna elements 208(1) to 208(6) and metal interconnects 240(1) to 240(3) that are of sufficient resolution to provide interconnects to the antenna elements 208(1) to 208(6). For example, antenna elements 208(1) to 208(6) can each support a wavelength less than, or equal to, one (1) mm.Antenna substrate 210 can be fabricated by stacking antenna layers 238(1) to 238(3) directly or not directly adjacent to the rear side 222 of RF IC 204 so that antenna elements 208(1) to 208(6) do not have to be formed in the BEOL 224 interconnect structure to minimize routing complexity in the BEOL 224 interconnect structure. Furthermore, it may be desirable to fabricate antenna substrate 210 directly or not directly adjacent to the rear side 222 of RF IC 204 so that the first, the clearance distance D2 between antenna elements 208(1) to 208(6) and RF circuits 206 can be controlled to reduce transmission loss in RF signals communicated by RF circuits 206 and the... Petition 870250089186, dated 10 / 01 / 2025, pp. 107 / 180 31 / 69 antenna elements 208(1) to 208(6) as discussed in more detail below.

[0041] For example, the first antenna layer 238(3) on the antenna substrate 210, in which the antenna elements 208(1) to 208(6) are formed, can be formed as a first redistribution layer (RDL) that includes metal interconnects 240(3) embedded in a respective dielectric material, insulating layer 242(3) of the first antenna layer 238(3). The second antenna layer 238(2) of the antenna layers 238(1) to 238(2) in this example is also a second RDL with its metal interconnects 240(2) embedded in an insulating layer 242(2) so that the antenna substrate 210 is a multilevel RDL. A non-limiting benefit of providing one or more of the antenna layers 238(2), 238(3), including the first antenna layer 238(3), as an RDL is the ability to redistribute signal routing on, and between, the antenna substrate 210 and the BEOL interconnect structure 224.For example, the first vias 244 are formed on the chip 200 to interconnect metal interconnects 240(1) in the antenna layer 238(1) to metal interconnects 228(4) in the first metal layer 226(4) in the BEOL interconnect structure 224. This provides a signal routing path between antenna elements 208(1) to 208(6) in the antenna substrate 210 and RF circuits 206 via metal interconnects 228(1) to 228(4) coupled to the first vias 244, to RF circuits 206. For example, the first vias 244 may be TSVs. The first 244 vias are arranged in a vertical direction (Z-axis direction) on chip 200, but through the RDLs on antenna layers 238(2), 238(3), the. Petition 870250089186, dated 10 / 01 / 2025, pp. 108 / 180 32 / 69 signal routing paths which include the first paths 244 can be redistributed in horizontal directions (X-axis and / or Y-axis directions) to be coupled to other metal interconnects 240(2) to 240(3) and the desired antenna element(s) 208(1) to 208(6).

[0042] Another non-limiting benefit of providing one or more of the antenna layers 238(2) to 238(3), including the first antenna layer 238(3), as an RDL, is to provide a reduced layer height in the vertical direction (Z-axis direction). This is partly because of the metal interconnections 240(2), 240(3) in the respective antenna layers. 238(2), 238(3) are incorporated into the respective insulating layers 242(2), 242(3). The process of forming the metal interconnects 240(2), 240(3) in the respective antenna layers 238(2), 238(3) as RDLs also allows the metal interconnects 240(2), 240(3) to be formed from a smaller L / S metal pattern and / or with a smaller pitch so that, for example, the antenna elements 208(1) to 208(6) can be made smaller to support shorter wavelengths to support higher RF frequencies and to provide the metal interconnects 240(2), 240(3) with a resolution fine enough to provide interconnections with antenna elements 208(1) to 208(6). For example, the metal interconnects 240(1) to 240(3) formed in the antenna layers 238(1) to 238(3) may have an L / S metal pattern of less than 3 pm. As another example, the pitch of the metal interconnects 240(1) to 240(3) formed in the antenna layers 238(1) to 238(3) may be less than five (5) pm and between 3.0 and 5.0 pm as another example. As yet another example, the antenna elements 208(1) to 208(2) may Petition 870250089186, dated 10 / 01 / 2025, pp. 109 / 180 33 / 69 to be manufactured in the first layer of antenna 238(3) to have dimensions in the horizontal directions (X-axis and Y-axis directions) that are less than or equal to 500 pm. For example, antenna elements 208(1) to 208(6) can be manufactured in the first layer of antenna 238(3) to have dimensions in the horizontal directions (X-axis and Y-axis directions) that are less than 1 millimeter (mm). As another example, antenna elements 208(1) to 208(6) can be dimensioned to be less than or equal to 500 pm to support higher frequencies. For example, to support D-band frequencies, antenna elements 208(1) to 208(6) can be dimensioned to be metal patch antennas of approximately 150 pm by 150 pm in the first layer of antenna 238(3).

[0043] As discussed above, the first, the clearance distance D2 between antenna elements 208(1) to 208(6) and RF circuits 206 can affect the transmission loss of RF signals between antenna elements 208(1) to 208(6) and RF circuits 206. As shown in Figure 2B, with the integration of antenna substrate 210 with RF IC 204 as part of wafer 200, the first, the clearance distance D2 can be reduced due to the ability to form antenna layers 238(1) to 238(2) on antenna substrate 210 of reduced height in the vertical direction (Z-axis direction). This is in comparison to an antenna substrate 102 as part of a package substrate 110 in antenna module 100 as an AiP in Figures 1A and 1B, which has a greater height in the vertical direction (Z-axis direction) than antenna substrate 210 in chip 200. For example, it may be desired that the first, the clearance distance D2 between Petition 870250089186, dated 10 / 01 / 2025, pp. 110 / 180 34 / 69 the antenna elements 208(1) to 208(6) and the RF circuits 206 are between seventy (70) and eighty (80) μm to support higher frequency RF signals.

[0044] In this example, not only to provide a substrate on which to form the antenna substrate 210 when manufacturing the wafer 200, but also to control the first, the clearance distance D2 between the antenna elements 208(1) to 208(6) and the RF circuits 206, a dielectric material substrate 250 is also provided in the wafer 200. The dielectric material substrate 250 is a dielectric material substrate that is disposed between the antenna substrate 210 and the RF IC 204 and, more particularly, the back side 222 of the RF IC 204 and its semiconductor layer 218, in the wafer 200. For example, the dielectric material substrate 250 could be a silicon substrate, which is a readily available material used in wafer-level processing and which can be used to form the dielectric material substrate 250 during wafer manufacturing. 200.A first thickness or first height H1 of the dielectric material substrate 250 can be controlled during the manufacture of the wafer 200 (e.g. by a milling process) to control the first, clearance distance D2 between the antenna elements 208(1) to 208(6) and the RF circuits 206. For example, the first height H1 of the dielectric material substrate 250 can be between 50 and 60 μm. For example, to achieve a first, clearance distance D2 between the antenna elements 208(1) to 208(6) and the RF circuits 206 between seventy (70) and eighty (80) μm to support higher frequency RF signals, the first height Hi of the dielectric material substrate 250. Petition 870250089186, dated 10 / 01 / 2025, pp. 111 / 180 The distance between antenna substrate 210 and the rear side 222 of RF IC 204 can be between 40 and 60 μm.

[0045] The permittivity of the dielectric substrate 250 can affect RF transmission losses in RF signals between RF circuits 206 and antenna elements 208(1) to 208(6). For example, the dielectric substrate 250 can be formed from a dielectric material such that it has a permittivity less than 6.0 farads per meter (F / m). The formation of the dielectric substrate 250 and the control of the selection of its dielectric material and manufacturing methods also make it possible to control the loss tangent and resistivity of the dielectric substrate 250 to control RF transmission losses. For example, the dielectric substrate 250 can be selected from a dielectric material and manufactured so that its loss tangent at 20 GHz is approximately 2 x 10-3.As another example, the dielectric substrate 250 can be selected from a dielectric material and manufactured so that its resistivity is greater than 107 Ohms / centimeter (cm). The antenna module 202 that is integrated into the wafer 200 can have several improvements, such as improved isolation between RF circuits 206 (e.g. >= 20 dB), the antennas 212 have an effective isotropic radiated power (EIRP) of approximately 2 dB, and with a reduction in total cost.

[0046] Figure 3 is a side view of an exemplary electronic device 300 which includes the wafer 200 as the antenna module 202 in Figures 2A and 2B coupled to a packet substrate 302. For example, the Petition 870250089186, dated 10 / 01 / 2025, pp. 112 / 180 36 / 69 package substrate 302 may include metallization layers 304 that provide signal routing paths to route signals to and from antenna module 202. Pad interconnects 306 (e.g., metal pads, micro-solder bumps, solder bumps formed in under-bump metallization pads (UBM)) are formed in contact with metal interconnects 228(1) in the metal layer 226(1) of the BEOL interconnect structure 224 which are then coupled to package substrate 302. Package substrate 302 may be a package substrate that includes metallization layers such as metallization substrate 116 in Figures 1A and 1B as examples.External interconnections 308 (e.g., solder protrusions, ball grid array (BGA) interconnections) are formed in contact with the package substrate 302 and can be coupled to a printed circuit board (PCB) 310 to electrically couple the antenna module 202 to the PCB 310 and to other electronic circuits coupled to the PCB 310.

[0047] Referring again to Figures 2A and 2B, the introduction of the dielectric material substrate 250 into the wafer 200 may cause an unintended consequence in RF transmission losses in RF signals between the RF circuits 206 and the antenna elements 208(1) to 208(6). The permittivity of the dielectric material substrate 250 may affect the RF transmission losses in RF signals between the RF circuits 206 and the antenna elements 208(1) to 208(6). For example, the dielectric material substrate 250 being formed from silicon as a substrate of Petition 870250089186, dated 10 / 01 / 2025, pp. 113 / 180 37 / 69 silicon may have a higher permittivity than FR4 or other material used to manufacture a package substrate, such as package substrate 110 in antenna module 100 in Figures 1A and 1B. Thus, although the introduction of dielectric material substrate 250 may assist in controlling the first, clearance distance D2 between antenna elements 208(1) to 208(6) and RF circuits 206 to be between seventy (70) and eighty (80) pm to support higher frequency RF signals, dielectric material substrate 250 may also contribute to RF transmission losses in RF signals between RF circuits 206 and antenna elements 208(1) to 208(6) in an unintended and undesirable way, which may cause antenna module 202 to be unable to support the desired frequency spectrum with sufficient performance.

[0048] In this sense, Figure 4 is a side view of another exemplary wafer 400 that provides an integrated antenna module 402 integrated into wafer 400 and that is capable of supporting higher frequency RF signals (e.g., D-band frequencies). However, wafer 400 is not required to support RF signals of any particular frequency or frequency band. Wafer 400 can be provided as part of a single IC chip 409 that is manufactured as part of a wafer-level fabrication process as an example. Common elements between wafer 400 in Figure 4 and wafer 200 in Figures 2A and 2B are shown with common element numbers, and will not be described again. However, in wafer 400 in Figure 4, a dielectric material substrate 450 is similar to the dielectric material substrate 250 in wafer 200 in Figures 2A and 2B. Petition 870250089186, dated 10 / 01 / 2025, pp. 114 / 180 38 / 69 is provided as a porous silicon substrate to control its permittivity. For example, during the manufacture of the 400 wafer, a porosification process can be performed on the 450 dielectric material substrate as a silicon substrate to control and tune its permittivity and loss tangent to desired levels to achieve the desired performance for the supported communication frequencies. Controlling the porosification of the 450 dielectric material substrate as a silicon substrate controls transmission losses between antenna elements 208(1) to 208(6) on antenna substrate 210 and RF IC 204. For example, the 450 dielectric material substrate as a porous silicon substrate can have a permittivity between 4 F / m and 6 F / m. As another example, the 450 dielectric material substrate as a porous silicon substrate can have a permittivity less than 6.0 F / m.

[0049] Also in this example of the 400 wafer in Figure 4, to avoid damaging the semiconductor layer 218 when performing the porosification process for the dielectric material substrate 450 as a silicon substrate, a stripping stop layer 452 (e.g., a nitride layer) can be placed on the dielectric material substrate 450 as a handle layer before forming the semiconductor layer 218 on it. The stripping stop layer 452 prevents porosification of the semiconductor layer 218 when the silicon substrate is processed into a porous silicon layer.

[0050] Figure 5 is a side view of another exemplary chip 500 which provides an integrated antenna module 502 integrated into the chip 500 which is capable of Petition 870250089186, dated 10 / 01 / 2025, pp. 115 / 180 39 / 69 supports higher frequency RF signals (e.g., D-band frequencies) similar to chip 400 in Figure 4. The 500 wafer can be provided as part of a single 509 IC chip that is manufactured as part of a wafer-level manufacturing process, for example. Common elements between the 500 wafer in Figure 5 and the 400 wafer in Figure 6 are shown with common element numbers and will not be described again. However, the 500 wafer in Figure 6 includes an RF IC 504 which is similar to the RF IC 204 in the 400 wafer in Figure 4. However, the RF IC 504 in the wafer The 500 in Figure 5 is a bulk device and not a SOI device. In Figure 5, the antenna substrate 210 of the 500 wafer is formed adjacent to a bulk semiconductor material layer such as the dielectric material substrate 450 (e.g., bulk silicon substrate) so that the 500 wafer is a bulk device. In this sense, the BOX layer 227 in the 400 wafer in Figure 4 is not present in the RF IC 504 in the 500 wafer in Figure 5. The RF IC 504 includes the semiconductor substrate 529 (e.g., silicon substrate) adjacent to the back side 222 of the semiconductor layer 218. Note also that although the 500 wafer in Figure 5 includes the dielectric material substrate 450 as a porous silicon substrate, this is not necessary. The 450 dielectric material substrate does not have to be a silicon substrate and it does not have to be a porous substrate.

[0051] There are several ways in which an antenna module that includes a chip that provides an antenna module, where the chip includes an RF IC with an RF circuit and an integrated antenna substrate to provide an antenna. Petition 870250089186, dated 10 / 01 / 2025, pp. 116 / 180 40 / 69 for the RF circuit, where the antenna substrate is adjacent to the rear side of the RF IC, including, but not limited to, the 200, 400, and 500 wafers in Figures 2A to 5, can be formed and manufactured. In this sense, Figure 6 is a flowchart illustrating an exemplary 600 manufacturing process for fabricating such a wafer. The 600 manufacturing process in Figure 6 is discussed in relation to the 200 wafer in Figures 2A and 2B, as an example, but this is not limiting.

[0052] In this sense, as shown in Figure 6, the manufacturing process 600 for forming the wafer 200 includes the formation of a semiconductor layer 218 (block 602 in Figure 6) which includes the first side 220, the back side 222 opposite the first side 220 and an RF circuit 206. The manufacturing process 600 also includes the formation of the BEOL interconnect structure 224 coupled to the RF circuit 206 for the wafer 200 (block 604 in Figure 6). The BEOL 224 interconnect structure comprises the front side 234 and the second side 236 opposite the front side 234. The second side 236 of the BEOL 224 interconnect structure is adjacent to the semiconductor layer 218. The second side 236 of the BEOL 224 interconnect structure is coupled to the semiconductor layer 218 and also adjacent to the RF circuit 206 in this example.The manufacturing process 600 of forming the 200 wafer may also include the formation of an antenna substrate 210 adjacent to the back side 222 of the semiconductor layer 218 (block 606 in Figure 6). The manufacturing process 600 of forming the 200 wafer may also include the formation of one or more first ways 244, each coupling an antenna element 208(1) to 208(6) of one or. Petition 870250089186, dated 10 / 01 / 2025, pp. 117 / 180 41 / 69 plus antenna elements 208(1) to 208(6) to the interconnect structure of BEOL 224 to couple one or more antenna elements 208(1) to 208(6) to the RF circuit 206 (block 608 in Figure 6).

[0053] Other manufacturing methods are also possible for manufacturing a wafer that provides an antenna module, wherein the wafer includes an RF IC with an RF circuit and an integrated antenna substrate to provide an antenna for the RF circuit, wherein the antenna substrate is adjacent to the rear side of the RF IC.For example, Figures 7A to 7E present a flowchart of another exemplary manufacturing process 700 for manufacturing a wafer like wafers 200, 400, 500 in Figures 2A to 5 and according to exemplary manufacturing stages 800A to 800F in Figures 8A to 8F, wherein the wafer is a SOI device with an RF circuit and an integrated antenna substrate to provide an antenna for the RF circuit, wherein the wafer additionally includes a layer of dielectric material disposed between a semiconductor layer of the RF IC and the antenna substrate to support the formation of the antenna substrate and to control the clearance distance between the antenna elements and the RF circuit to control transmission losses, including, but not limited to, wafers 200, 400, 500 in Figures 2A to 5.The manufacturing stages 800A to 800F in Figures 8A to 8F, according to the exemplary manufacturing process 700 in Figures 7A to 7E, will now be discussed in relation to the 400 wafer in Figure 4, as a non-limiting example of an SOI device.

[0054] In this sense, as shown in the exemplary manufacturing stage 800A in Figure 8A, a first Petition 870250089186, dated 10 / 01 / 2025, pages 118 / 180 Step 42 / 69 in the manufacturing process 700 is to provide a starting wafer 802 in which the processing and accumulation of layers occurs to form the pellet 400 (block 702 in Figure 7A). Note that the starting pellet 802, after being completely processed and its layers are fully formed, will be cut into separate pellets, which will be like the pellet 400 in Figure 4.

[0055] In this regard, as shown in the exemplary fabrication stage 800A in Figure 8A, the fabrication process 700 includes the formation of a dielectric material substrate 804 (before being processed to form the dielectric material substrate 450 in Figure 4), which can be a silicon substrate (block 702 in Figure 7A). Furthermore, as shown in the fabrication stage 800A in Figure 8A, the stripping stop layer 452 is formed on the dielectric material substrate 804 (block 702 in Figure 7A). As previously discussed, the stripping stop layer 452 is to protect the RF IC 204 from being damaged during the porosification of the dielectric material substrate 804 in a subsequent processing step to control its permittivity. For example, the stripping stop layer 452 can be formed from silicon nitride. As an example, the 452 pickling stop layer can be 1000 Angstroms (A) thick.Furthermore, as shown in fabrication stage 800A in Figure 8A, semiconductor layers in the form of BOX layer 227 and an insulating layer 806 are formed in the stripping stop layer 452 as part of the semiconductor layer 218 to be formed to form active components (block 702 in Figure 7A). Petition 870250089186, dated 10 / 01 / 2025, pp. 119 / 180 43 / 69

[0056] Next, as shown in the exemplary fabrication stage 800B in Figure 8B, the semiconductor layer 218 of RF IC 204 is formed as part of a FEOL fabrication process (block 704 in Figure 7A). RF circuits 206 are formed on semiconductor layer 218 (block 704 in Figure 7A). The BEOL interconnect structure 224 is also formed as part of a BEOL fabrication process adjacent to semiconductor layer 218 to form RF IC 204 (block 704 in Figure 7A). This process is part of a CMOS fabrication process in this example.

[0057] Next, as shown in exemplary fabrication stage 800C in Figure 8C, a temporary handle wafer 808 (handle wafer 808) is bonded to the RF IC 204 adjacent to the BEOL 224 interconnect structure (block 706 in Figure 7B). This is so that the starting wafer 802 can be handled to process the dielectric material substrate 450 to control its first definite height H1 to control the clearance distance between the RF circuits 206 and the antenna elements 208(1) to 208(6) on the antenna substrate 210 to be integrated as part of a wafer 400. For example, the dielectric material substrate 450 can be milled to control its first definite height H1 (block 706 in Figure 7B). As an example, the dielectric material substrate 450 can be milled so that its first height Hi is between 50 and 60 gm. Then, as shown in the exemplary fabrication stage 800D in Figure 8D, a hard mask layer 810 is formed on the loop wafer 808 (block 708 in Figure 7C) to protect the starting wafer 802 when the dielectric material substrate 450 is subsequently subjected to a Petition 870250089186, dated 10 / 01 / 2025, pages 120 / 180 44 / 69 porosification process to make the dielectric material substrate 450 porous (e.g., a porous silicon) to control its permittivity. For example, the hard mask layer 810 can be a low-pressure chemical vapor deposition (LPCVD) silicon nitride layer.

[0058] Next, as shown in exemplary fabrication stage 800E in Figure 8E, a porosification process is performed on the dielectric material substrate 450 to make the dielectric material substrate 450 a porous substrate to control its permittivity (block 710 in Figure 7D). The amount of porosity added to the dielectric material substrate 450 controls its permittivity. For example, the dielectric material substrate 450 can be converted into a porous substrate by subjecting the dielectric material substrate 450 to an electrolytic pickling process in hydrofluoric acid (HF) with ethanol. The electrolytic pickling stops at the pickling stop layer 452. Furthermore, as shown in fabrication stage 800E in Figure 8E, the hard mask layer 810 and the handle wafer 808 are removed (block 710 in Figure 7D).

[0059] Next, as shown in the exemplary fabrication stage 800F in Figure 8F, the antenna substrate 210 is formed on the dielectric material substrate 450 (block 712 in Figure 7E). The antenna substrate 210 can be built on the dielectric material substrate 450 in separate antenna layers 238(1) to 238(3) (see Figure 4) which can be RDL layers as previously described. The antenna layers 238(1) to 238(3) can be formed and Petition 870250089186, dated 10 / 01 / 2025, pages 121 / 180 45 / 69 are accumulated as RDL layers in a photopolyimide material on the dielectric material substrate 450. Antenna elements 208(1) to 208(6) are formed in the first antenna layer 238(3). Furthermore, as shown in the exemplary fabrication stage 800F in Figure 8F, the first vias 244 are formed through the dielectric material substrate 450, the stripping stop layer 452 and the RF IC 204 to couple metal interconnects 240(1) in the antenna layer 238(1) to metal interconnects 228(4) in the BEOL interconnect structure 224 (block 712 in Figure 7E). As an example, the first vias 244 can be formed by a punching process. The first 244 pathways provide signal routing paths between antenna elements 208(1) to 208(6) on antenna substrate 210 and the BEOL interconnect structure 224 to then provide these signal routing paths to RF circuits 206 on RF IC 204.

[0060] Figures 9A to 9E present a flowchart of another exemplary manufacturing process 900 for manufacturing a wafer similar to wafer 500 as a bulk device in Figure 5 and according to exemplary manufacturing stages 1000A to 1000F in Figures 10A to 10F. Manufacturing stages 1000A to 1000F in Figures 10A to 10F, according to exemplary manufacturing process 900 in Figures 9A to 9E, will now be discussed in relation to wafer 500 in Figure 5, as a non-limiting example.

[0061] In this sense, as illustrated in the exemplary manufacturing stage 1000A in Figure 10A, a first step in the manufacturing process 900 is to provide a Petition 870250089186, dated 10 / 01 / 2025, pp. 122 / 180 46 / 69 starting wafer 1002 to process and accumulate layers to form wafer 500 (block 902 in Figure 9A). Note that the starting wafer 1002, after being fully processed once its layers are fully formed, will be cut into separate wafers, which will be like wafer 500 in Figure 5. As shown in the exemplary fabrication stage 1000A in Figure 10A, the fabrication process 900 includes the formation of a dielectric material substrate 1004, which can be a silicon substrate (block 902 in Figure 9A). Furthermore, as shown in the fabrication stage 1000A in Figure 10A, the stripping stop layer 452 is formed on the dielectric material substrate 1004 (block 902 in Figure 9A).As previously discussed, the stripping stop layer 452 serves to protect the RF IC 504 from being damaged during the porosification of the dielectric material substrate 1004 in a subsequent processing step to control its permittivity. For example, the stripping stop layer 452 can be formed from silicon nitride. As an example, the stripping stop layer 452 can be 1000 Å thick. Furthermore, as shown in the 1000 Å fabrication stage in Figure 10A, semiconductor layers in the form of a silicon substrate 1006 are formed on the stripping stop layer 452 as part of the semiconductor layer 218 to be formed to create active components (block 902 in Figure 9A).

[0062] Next, as shown in exemplary fabrication stage 1000B in Figure 10B, the 218 semiconductor layer of RF IC 504 is formed as part of a FEOL fabrication process (block 904 in Figure 9A). The Petition 870250089186, dated 10 / 01 / 2025, pp. 123 / 180 47 / 69 RF 206 circuits are formed in the semiconductor layer (block 904 in Figure 9A). The BEOL 224 interconnect structure is also formed as part of a BEOL fabrication process adjacent to the semiconductor layer 218 to form the RF IC 504 (block 904 in Figure 9A). This process is part of a CMOS fabrication process in this example.

[0063] Next, as shown in exemplary manufacturing stage 1000C in Figure 10C, a temporary handle wafer 1008 (handle wafer 1008) is bonded to RF IC 504 adjacent to the BEOL 224 interconnect structure (block 906 in Figure 9B). This is so that the starting wafer 1002 can be handled to process the dielectric material substrate 450 to control its first definite height H1 to control the clearance distance between the RF circuits 206 and the antenna elements 208(1) to 208(6) on the antenna substrate 210 to be integrated as part of the wafer 500. For example, the dielectric material substrate 450 can be milled to control its first definite height H1 (block 906 in Figure 9B). As an example, the 450 dielectric substrate can be milled so that its first height Hi is between 50 and 60 μm.

[0064] Next, as shown in exemplary fabrication stage 1000D in Figure 10D, a hard mask layer 1010 is formed on the handle wafer 1008 (block 908 in Figure 9C) to protect the starting wafer 1002 when the dielectric material substrate 450 is subsequently subjected to a porosification process to make the dielectric material substrate 450 porous (e.g., a porous silicon) to control its permittivity. For example, the hard mask layer 1010 could be a layer Petition 870250089186, dated 10 / 01 / 2025, pp. 124 / 180 48 / 69 low-pressure chemical vapor deposition (LPCVD) silicon nitride.

[0065] Next, as shown in exemplary fabrication stage 1000E in Figure 10E, a porosification process is performed on the dielectric material substrate 450 to make the dielectric material substrate 450 a porous substrate to control its permittivity (block 910 in Figure 9D). The amount of porosity added to the dielectric material substrate 450 controls its permittivity. For example, the dielectric material substrate 450 can be converted into a porous substrate by subjecting the dielectric material substrate 450 to an electrolytic pickling process in hydrofluoric acid (HF) with ethanol. Electrolytic pickling stops at the pickling stop layer 452. Furthermore, as shown in fabrication stage 1000E in Figure 10E, the hard mask layer 1010 and the handle wafer 1008 are removed (block 910 in Figure 9D).

[0066] Next, as shown in exemplary fabrication stage 1000F in Figure 10F, antenna substrate 210 is formed on dielectric material substrate 450 (block 912 in Figure 9E). Antenna substrate 210 can be built on top of dielectric material substrate 450 in separate antenna layers 238(1) to 238(3) (shown in Figure 5) which can be RDL layers as previously described. Antenna layers 238(1) to 238(3) can be formed and stacked as RDL layers in a photopolyimide material on dielectric material substrate 450. Antenna elements 208(1) to 208(6) are formed on the first antenna layer 238(3). Furthermore, as shown in Petition 870250089186, dated 10 / 01 / 2025, pages 125 / 180 49 / 69 exemplary fabrication stage 1000F in Figure 10F, the first vias 244 are formed through the dielectric substrate 450, the stripping stop layer 452 and the RF IC 504 to couple metal interconnects 240(1) in the antenna layer 238(1) to metal interconnects 228(4) in the BEOL interconnect structure 224 (block 912 in Figure 9E). As an example, the first vias 244 can be formed by a drilling process. The first vias 244 provide signal routing paths between antenna elements 208(1) to 208(6) in the antenna substrate 210 and the BEOL interconnect structure 224 to then provide these signal routing paths to the RF circuits. 206 in RF IC 504.

[0067] Note that the examples of the 200, 400, 500 chips in Figures 2A to 5, 8F and 10F discussed above refer to their respective 212 antennas being capable of supporting particular exemplary frequencies and / or frequency bands, including in the D-band frequency spectrum. Note that the 212 antennas are not so limited. The 212 antennas formed on the 200, 400, 500 chips in Figures 2A to 5, 8F and 10F and / or any other chip providing an antenna module, wherein the chip includes an RF IC with an RF circuit and an integrated antenna substrate to provide an antenna for the circuit of RF devices can be designed and manufactured to support any desired frequencies and / or frequency spectrum, including, without limitation, frequency spectrum in 5G and 6G bands and lower and higher frequencies.

[0068] An object being in an adjacent position, as discussed in the present invention, refers to a Petition 870250089186, dated 10 / 01 / 2025, pp. 126 / 180 50 / 69 object being next to or near another mentioned object. Objects in adjacent positions may not be directly and physically coupled to each other. An object may be directly adjacent to another object, meaning that such objects are directly next to or near the other object without another object or layer intervening or being placed between the directly adjacent objects. An object may be indirectly or not directly adjacent to another object, meaning that such objects are not directly next to or directly near each other, but there is an intervening object or layer placed between the non-directly adjacent objects.

[0069] A wafer providing an antenna module, wherein the wafer includes an RF IC with an RF circuit and an integrated antenna substrate to provide an antenna for the RF circuit, wherein the wafer further includes a layer of dielectric material disposed between a semiconductor layer of the RF IC and the antenna substrate to support the formation of the antenna substrate and to control the clearance distance between the antenna elements and the RF circuit to control transmission losses, including, but not limited to, wafers 200, 400, 500 in Figures 2A to 5, 8F and 10F, and which may be manufactured according to any of the exemplary manufacturing processes 600, 700, 900 in Figures 6, 7A to 7E and 9A to 9E, may be provided or integrated into any wireless communication device and / or processor-based device. Examples, without limitation, include a set-top box, an entertainment unit, a navigation device, a device Petition 870250089186, dated 10 / 01 / 2025, pp. 127 / 180 51 / 69 communications, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cell phone, a smartphone, a session initiation protocol (SiP) phone, a tablet, a phablet, a server, a computer, a laptop, a mobile computing device, a wearable computing device (e.g., a smartwatch, a health or fitness monitor device, glasses, etc.).a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, avionics systems, a drone, and a multicopter.

[0070] Figure 11 illustrates an exemplary wireless communication device 1100 that includes an antenna module 1102. The antenna module 1102 is provided in the form of a wafer 1103 that includes an RF IC with an RF circuit and an integrated antenna substrate to provide an antenna for the RF circuit, wherein the antenna substrate is adjacent to the rear side of the RF IC. The wafer 1103 may include wafers 200, 400, 500 in Figures 2A to 5, 8F or 10F and be manufactured according to any of the manufacturing processes 600, 700, 900 in Figures 6, 7A to 7E or 9A to 9E, Petition 870250089186, dated 10 / 01 / 2025, pp. 128 / 180 52 / 69 as non-limiting examples. As shown in Figure 11, the wireless communication device 1100 includes an RF transceiver 1104 and a data processor 1106. The components of the RF transceiver 1104 and / or the data processor 1106 can be divided among multiple different chips 1105(1), 1105(2). The data processor 1106 may include a memory for storing data and program codes. The RF transceiver 1104 includes a transmitter 1108 and a receiver 1110 that support bidirectional communications. In general, the wireless communication device 1100 may include any number of transmitters 1108 and / or receivers 1110 for any number of communication systems and frequency bands. All or part of the 1104 RF transceiver can be implemented in one or more analog ICs, RF ICs, mixed-signal ICs, etc.

[0071] The 1108 transmitter or the 1110 receiver can be implemented with a superheterodyne architecture or a direct conversion architecture. In the superheterodyne architecture, a signal is frequency converted between RF and baseband in multiple stages, for example, from RF to an intermediate frequency (IF) in one stage and then from IF to baseband in another stage, for the 1110 receiver. In the direct conversion architecture, the frequency of a signal is converted between RF and baseband in one stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. In the 1100 wireless communication device in Figure 11, the 1108 transmitter and the 1110 receiver are implemented with the direct conversion architecture. Petition 870250089186, dated 10 / 01 / 2025, pp. 129 / 180 53 / 69

[0072] In the transmission path, the data processor 1106 processes the data to be transmitted and provides analog output signals I and Q to the transmitter 1108. In the exemplary wireless communication device 1100, the data processor 1106 includes digital-to-analog converters (DACs) 1112(1), 1112(2) to convert digital signals generated by the data processor 1106 into analog output signals I and Q, for example, output currents I and Q, for further processing.

[0073] In transmitter 1108, low-pass filters 1114(1), 1114(2) filter the analog output signals I and Q, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 1116(1), 1116(2) amplify the signals from low-pass filters 1114(1), 1114(2), respectively, and provide the baseband signals. I and Q. An upconverter 1118 upconverts the baseband signals I and Q with local oscillator (LO) signals from transmission (TX) I and Q, through mixers 1120(1), 1120(2) from a TX LO signal generator 1122 to provide an upconverted signal 1124. A filter 1126 filters the upconverted signal 1124 to remove unwanted signals caused by the frequency upconversion, as well as noise in a receiving frequency band. A power amplifier (PA) 1128 amplifies the upconverted signal 1124 from the filter 1126 to obtain the desired output power level and provide a transmission RF signal. The Petition 870250089186, dated 10 / 01 / 2025, pages 130 / 180 The 54 / 69 RF transmission signal is routed through a duplexer or switch 1130 and transmitted via an antenna 1132.

[0074] In the receiving path, antenna 1132 receives signals transmitted by base stations and provides a received RF signal, which is routed through duplexer or switch 1130 and provided to a low noise amplifier (LNA) 1134. Duplexer or switch 1130 is designed to operate with a specific frequency separation from the receiving (RX) to transmitting (TX) duplexer, so that RX signals are isolated from TX signals. The received RF signal is amplified by LNA 1134 and filtered by a filter 1136 to obtain a desired RF input signal. Downconversion mixers 1138(1), 1138(2) mix the output of filter 1136 with LO signals from RX I and Q (i.e., LO_I and LO_Q) coming from an LO signal generator from RX 1140 to generate the baseband signals I and Q.The baseband signals I and Q are amplified by AMPs 1142(1), 1142(2) and further filtered by low-pass filters 1144(1), 1144(2) to obtain the analog input signals I and Q, which are provided to the data processor 1106. In this example, the data processor 1106 includes analog-to-digital converters (ADCs) 1146(1), 1146(2) to convert the analog input signals into digital signals to be further processed by the data processor 1106.

[0075] In the wireless communication device 1100 of Figure 11, the TX LO signal generator 1122 generates the TX LO signals I and Q used for frequency upconversion, while the RX LO signal generator Petition 870250089186, dated 10 / 01 / 2025, pp. 131 / 180 55 / 69 1140 generates the RX LO signals I and Q used for frequency downconversion. Each LO signal is a periodic signal with a particular fundamental frequency. A phase-locked loop (PLL) circuit of TX 1148 receives timing information from data processor 1106 and generates a control signal used to adjust the frequency and / or phase of the TX LO signals from the TX LO signal generator 1122. Similarly, a PLL circuit of RX 1150 receives timing information from data processor 1106 and generates a control signal used to adjust the frequency and / or phase of the RX LO signals from the RX LO signal generator 1140.

[0076] Figure 12 illustrates an example of a 1200 processor-based system that may include an antenna module in the form of a 1202 chip, 1202(1) to 1202(6). The 1202, 1202(1) to 1202(6) chip includes an RF IC with an RF circuit and an integrated antenna substrate to provide an antenna for the RF circuit, wherein the antenna substrate is adjacent to the rear side of the RF IC. The 1202, 1202(1) to 1202(6) chip may include the 200, 400, 500 in Figures 2A to 5, 8F or 10F and be manufactured according to any of the manufacturing processes 600, 700, 900 in Figures 6, 7A to 7E or 9A to 9E are examples that are not limiting.

[0077] In this example, the processor-based system 1200 can be formed as a system-on-a-chip (SoC) 1206 that includes the chip 1202. The processor-based system 1200 includes a CPU 1208 that includes one or more processors 1210, which may also be called CPU cores or processor cores. The CPU 1208 may have a cache memory 1212 coupled to the CPU 1208. Petition 870250089186, dated 10 / 01 / 2025, pp. 132 / 180 56 / 69 for fast access to temporarily stored data. The CPU 1208 is coupled to a system bus 1214 and can intercouple master and slave devices included in the processor-based system 1200. As is well known, the CPU 1208 communicates with these other devices by exchanging address, control, and data information through the system bus 1214. For example, the CPU 1208 can communicate bus transaction requests to a memory controller 1216 as an example of a slave device. Although not illustrated in Figure 12, multiple system buses 1214 could be provided, where each system bus 1214 constitutes a different mesh. The CPU 1208 can contain the chip 1202(1).

[0078] Other master and slave devices may be connected to the system bus 1214. As illustrated in Figure 12, these devices may include a memory system 1220 (which may contain chip 1202(2)) which includes the memory controller 1216 and memory array(s) 1218, one or more input devices 1222 (which may contain chip 1202(3)), one or more output devices 1224 (which may contain chip 1202(4)), one or more network interface devices 1226 (which may contain chip 1202(5)) and one or more display controllers 1228 (which may contain chip 1202(6)), as examples. Each of the memory systems 1220, the one or more input devices 1222, the one or more output devices 1224, the one or more network interface devices 1226, and the one or more display controllers 1228 may be provided in the same IC package or in different packages. The input device(s) 1222 may include any Petition 870250089186, dated 10 / 01 / 2025, pp. 133 / 180 57 / 69 Input device type, including but not limited to input keys, switches, voice processors, etc. Output device(s) 1224 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface device(s) 1226 may be any device configured to enable data exchange to and from a network 1230. Network 1230 may be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The 1226 network interface device(s) can be configured to support any desired communication protocol type.

[0079] The CPU 1208 can also be configured to access the display controller(s) 1228 via the system bus 1214 to control information sent to one or more displays 1232. The display controller(s) 1228 send(s) information to the display(s) 1232 to be displayed via one or more video processors. 1234, which process the information to be displayed in a format suitable for the display(s) 1232. The display controller(s) 1228 and video processor(s) 1234 may be included in identical or different IC packages, and in identical or different IC packages containing the CPU 1208 as an example. The display(s) 1232 may include any type of display, including, but not limited to, Petition 870250089186, dated 10 / 01 / 2025, pp. 134 / 180 58 / 69 limiting to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.

[0080] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed in the present invention can be implemented as electronic hardware, instructions stored in memory or other computer-readable media, and executed by a processor or other processing device, or combinations thereof. The memory disclosed in the present invention can be any type and size of memory, and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generically in terms of their functionality. The manner in which such functionality is implemented depends on the particular application, design choices, and / or design constraints imposed on the system as a whole.Subject matter experts may implement the described functionality in various ways for each particular application, but such implementation decisions should not be interpreted as deviating from the scope of this disclosure.

[0081] The various logic blocks, modules and illustrative circuits described in connection with the aspects disclosed in the present invention can be implemented or realized with a processor, a signal processor Petition 870250089186, dated 10 / 01 / 2025, pages 135 / 180 59 / 69 digital signal processors (DSPs), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described in the present invention. A processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0082] The aspects disclosed in the present invention can be incorporated into hardware and instructions that are stored in hardware and may reside, for example, in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, a hard disk, a removable disk, a CD-ROM, or any other form of computer-readable media known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from, and write information from Petition 870250089186, dated 10 / 01 / 2025, pages 136 / 180 60 / 69 no, storage medium. Alternatively, the storage medium may be an integral part of the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, a base station, or a server.

[0083] It should also be mentioned that the operational steps described in any of the exemplary aspects of the present invention are described to provide examples and discussion. The operations described can be performed in numerous different sequences beyond the sequences illustrated. Furthermore, the operations described in a single operational step can effectively be performed in several different steps. Additionally, one or more operational steps discussed in the exemplary aspects can be combined. It should be understood that the operational steps illustrated in the flowchart diagrams may be subject to numerous different modifications, as will be readily apparent to those skilled in the art. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different technologies and techniques.For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the description above can be represented by voltages, currents, electromagnetic waves, magnetic particles or fields, optical particles or fields, or any combination thereof. Petition 870250089186, dated 10 / 01 / 2025, pp. 137 / 180 61 / 69

[0084] The preceding description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined in the present invention can be applied to other variations. Thus, the disclosure is not intended to be limited to the examples and designs described in the present invention, but rather to be given the broadest scope consistent with the innovative principles and attributes disclosed in the present invention.

[0085] Examples of implementations are described in the following numbered clauses: 1. A semiconductor wafer comprising: a semiconductor layer comprising: a first side; a rear side opposite the first side; and a radio frequency (RF) circuit; a back-end line interconnect (BEOL) structure coupled to the RF circuit, wherein the BEOL interconnect structure comprises: a front side; and a second side opposite the front side, the second side coupled to the first side of the semiconductor layer; an antenna substrate adjacent to the rear side of the semiconductor layer; wherein the antenna substrate comprises one or more antenna layers, a first antenna layer of the one or more antenna layers comprising one or more antenna elements; and Petition 870250089186, dated 10 / 01 / 2025, pp. 138 / 180 62 / 69 one or more first paths, each coupling one antenna element from the one or more antenna elements to the BEOL interconnect structure to couple the one or more antenna elements to the RF circuit. 2. The semiconductor wafer of clause 1, wherein the first antenna layer comprises a metal layer comprising one or more metal structures comprising one or more antenna elements. 3. The semiconductor wafer of clause 2, where the first antenna layer has a metal pattern with a line spacing (L / S) of less than 3 pm. 4. The semiconductor wafer of any of clauses 1 to 3, wherein the first antenna layer comprises a first redistribution layer (RDL). 5. The semiconductor wafer of any of clauses 1 to 3, wherein one or more antenna layers each comprise a redistribution layer (RDL). 6. The semiconductor chip of any of clauses 1 to 5, wherein one or more antenna elements comprise one or more metal patch antennas. 7. A semiconductor wafer of any of the clauses 1 to 6, wherein each dimension of one or more antenna elements is less than or equal to 500 micrometers (µm). 8. The semiconductor wafer of any of clauses 1 to 7, wherein one or more antenna elements each support a wavelength less than or equal to one (1) millimeter (mm). 9. The semiconductor chip of any of the clauses 1 to 8, in which one or more antenna elements Petition 870250089186, dated 10 / 01 / 2025, pp. 139 / 180 63 / 69 each support at least one communication frequency between 110 and 170 gigahertz (GHz). 10. The semiconductor wafer of any of clauses 1 to 9, which additionally comprises a dielectric material substrate between the back side of the semiconductor layer and the antenna substrate. 11. The semiconductor wafer of clause 10, which further comprises a stripping stop layer between the dielectric material substrate and the semiconductor layer. 12. The semiconductor wafer of clause 10 or 11, wherein the dielectric material substrate comprises a silicon substrate. 13. The semiconductor wafer of clause 12, wherein the silicon substrate comprises a porous silicon substrate. 14. A semiconductor wafer of any clause 10 to 13, in which the dielectric substrate has a permittivity between 4 farads per meter (F / m) and 6 F / m. 15. A semiconductor wafer of any of clauses 10 to 14, wherein the dielectric substrate has a permittivity less than or equal to 5.0 farads per meter (F / m). 16. A semiconductor wafer of any of clauses 10 to 15, wherein the dielectric substrate has a first thickness between the antenna substrate and the semiconductor layer between 40 and 60 micrometers (µm). 17. The semiconductor chip of any of the clauses 1 to 16, in which one or more antenna elements Petition 870250089186, dated 10 / 01 / 2025, pp. 140 / 180 64 / 69 are each positioned at an initial distance from the RF circuit between seventy (70) and eighty (80) micrometers (gm). 18. The semiconductor wafer of any of clauses 1 to 17, which further comprises an integrated circuit (IC) comprising the semiconductor layer and the BEOL interconnect structure; wherein the IC comprises a bulk device, in which the semiconductor layer comprises a layer of bulk semiconductor material. 19. The semiconductor chip of any of clauses 1 to 17, which additionally comprises: an integrated circuit (IC) comprising a silicon-on-insulator (SOI) device comprising the semiconductor layer and the BEOL interconnect structure; wherein the semiconductor layer comprises a buried oxide layer (BOX) adjacent to the front side and a semiconductor substrate adjacent to the back side, such that the BOX layer is between the front side and the semiconductor substrate. 20. The semiconductor chip of any of the clauses 1 to 19, where: The BEOL interconnection structure comprises a plurality of metal layers between the front side and the second side, each of the metal layers comprising one or more metal interconnections; and each of the first two ways couples an antenna element to the antenna elements. Petition 870250089186, dated 10 / 01 / 2025, pp. 141 / 180 65 / 69 one or more metal interconnections in a first metal layer among a plurality of metal layers; and further comprising: one or more duplicates, each coupled to the RF circuit and each coupled to one or more metal interconnects in the first metal layer among the plurality of metal layers. 21. The semiconductor wafer of any of clauses 1 to 20, wherein one or more first ways comprise one or more first ways through silicon (TSVs). 22. The semiconductor chip of any of clauses 1 to 21 integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a Session Initiation Protocol (SiP) phone; a tablet; a phablet; a server; a computer; a laptop computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player;a digital video disc (DVD) player; a player of; Petition 870250089186, dated 10 / 01 / 2025, pp. 142 / 180 66 / 69 portable digital video; an automobile; a vehicle component; avionics systems; a drone; and a multicopter. 23. A method for manufacturing a semiconductor wafer comprising: to form a semiconductor layer comprising: a first side; a rear side opposite the first side; and a radio frequency (RF) circuit; to form a back-end line interconnection (BEOL) structure coupled to the RF circuit, wherein the BEOL interconnection structure comprises: a front side; and a second side opposite the front side, the second side coupled to the semiconductor layer; to form an antenna substrate adjacent to the rear side of the semiconductor layer, comprising: to form one or more antenna layers, wherein a first antenna layer of the one or more antenna layers comprises one or more antenna elements; and to form one or more first paths, each coupling one antenna element of the one or more antenna elements to the BEOL interconnect structure to couple the one or more antenna elements to the RF circuit. 24. The method of clause 23, wherein the formation of one or more antenna layers comprises the formation of the first antenna layer comprising the formation of a metal layer comprising one or more metal structures comprising the one or more antenna elements in the first antenna layer. Petition 870250089186, dated 10 / 01 / 2025, pp. 143 / 180 67 / 69 25. The method of clause 23 or 24, in which the formation of the metal layer comprises the formation of a first redistribution layer (RDL). 26. The method of any of clauses 23 to 25, which further comprises the formation of a dielectric material substrate adjacent to the back side of the semiconductor layer; and wherein the formation of the antenna substrate further comprises the formation of the antenna substrate on the dielectric material substrate. 27. The method of clauses 23 to 25, which additionally includes: to form a dielectric material substrate adjacent to the back side of the semiconductor layer; and to form a stripping stop layer on the dielectric material substrate; wherein the formation of the antenna substrate additionally comprises the formation of the antenna substrate adjacent to the stripping stop layer. 28. The method of clause 26 or 27, in which the formation of the dielectric substrate additionally comprises: to form a silicon substrate adjacent to the back side of the semiconductor layer; and to porosify the silicon substrate to form a porous silicon substrate adjacent to the back side of the semiconductor layer. 29. The method of any of clauses 23 to 28, in which the formation of the BEOL interconnection structure additionally comprises the formation of a plurality of Petition 870250089186, dated 10 / 01 / 2025, pp. 144 / 180 68 / 69 metal layers between the front side and the second side, the plurality of metal layers each comprising one or more metal interconnects; and further comprising forming one or more first ways in the antenna substrate and in the BEOL interconnect structure, each coupling an antenna element of the one or more antenna elements to one or more metal interconnects in a first metal layer among the plurality of metal layers. 30. The method of clause 29, which further comprises forming one or more duplicates, each coupled to the RF circuit and each coupled to one or more metal interconnections in the first metal layer among the plurality of metal layers. 31. The method of clause 29 or 30, wherein the formation of one or more first ways comprises the formation of one or more first ways through silicon (TSVs) in the antenna substrate and in the BEOL interconnect structure, each coupling one antenna element of the one or more antenna elements to one or more metal interconnects in the first metal layer among the plurality of metal layers. 32. The method described in any of clauses 26 to 31, which further comprises grinding the dielectric material substrate to a first desired thickness to control a distance between one or more antenna elements and the RF circuit. 33. The method of any of clauses 26 to 32, in which the formation of the semiconductor layer additionally comprises: Petition 870250089186, dated 10 / 01 / 2025, pp. 145 / 180 69 / 69 to form a semiconductor substrate on the dielectric material substrate, the semiconductor substrate comprising the back side; and to form a buried oxide layer (BOX) on the semiconductor substrate; in which: Forming the BEOL interconnection structure additionally involves forming the BEOL interconnection structure adjacent to the BOX layer. 34. The method of any of clauses 26 to 32, wherein the formation of the semiconductor layer further comprises the formation of a silicon layer on the dielectric substrate, wherein the silicon layer comprises the front side and the back side; and wherein: Forming the BEOL interconnect structure additionally involves forming the BEOL interconnect structure adjacent to the silicon layer. Petition 870250089186, dated 10 / 01 / 2025, pages 146 / 180

Claims

1 / 9 CLAIMS 1. Semiconductor wafer characterized in that it comprises: a semiconductor layer comprising: a first side; a rear side opposite the first side; and a radio frequency (RF) circuit; a back-end line interconnect structure (BEOL) coupled to the RF circuit, wherein the BEOL interconnect structure comprises: a front side; and a second side opposite the front side, the second side coupled to the first side of the semiconductor layer; an antenna substrate adjacent to the rear side of the semiconductor layer; wherein the antenna substrate comprises one or more antenna layers, a first antenna layer of the one or more antenna layers comprising one or more antenna elements; and one or more first vias, each coupling one antenna element of the one or more antenna elements to the BEOL interconnect structure for coupling the one or more antenna elements to the RF circuit.

2. Semiconductor wafer, according to claim 1, characterized in that the first antenna layer comprises a metal layer comprising one or more metal structures comprising one or more antenna elements. Petition 870250089186, dated 10 / 01 / 2025, pp. 147 / 180 2 / 9 3. Semiconductor wafer, according to claim 2, characterized in that the first antenna layer has a metal line spacing (L / S) pattern of less than 3 pm.

4. Semiconductor wafer, according to claim 1, characterized in that the first antenna layer comprises a first redistribution layer (RDL).

5. Semiconductor wafer, according to claim 1, characterized in that one or more antenna layers each comprise a redistribution layer (RDL).

6. Semiconductor wafer, according to claim 1, characterized in that one or more antenna elements comprise one or more metal patch antennas.

7. Semiconductor wafer, according to claim 1, characterized in that each dimension of one or more antenna elements is less than or equal to 500 micrometers (µm).

8. Semiconductor wafer, according to claim 1, characterized in that one or more antenna elements each support a wavelength less than or equal to one (1) millimeter (mm).

9. Semiconductor wafer, according to claim 1, characterized in that one or more antenna elements each support at least one communication frequency between 110 and 170 gigahertz (GHz).

10. Semiconductor wafer, according to claim 1, characterized in that it further comprises a dielectric material substrate between the back side of the semiconductor layer and the antenna substrate.

11. Semiconductor wafer, according to claim 10, characterized in that it further comprises a stripping stop layer between the dielectric material substrate and the semiconductor layer.

12. Semiconductor wafer, according to claim 10, characterized in that the dielectric material substrate comprises a silicon substrate.

13. Semiconductor wafer, according to claim 12, characterized in that the silicon substrate comprises a porous silicon substrate.

14. Semiconductor wafer, according to claim 10, characterized in that the dielectric material substrate has a permittivity between 4 farads per meter (F / m) and 6 F / m.

15. Semiconductor wafer, according to claim 10, characterized in that the dielectric material substrate has a permittivity less than or equal to 5.0 farads per meter (F / m).

16. Semiconductor wafer, according to claim 10, characterized in that the dielectric material substrate has a first thickness between the antenna substrate and the semiconductor layer between 40 and 60 micrometers (µm).

17. Semiconductor wafer, according to claim 1, characterized in that one or more antenna elements are each arranged at a first distance from the RF circuit between seventy (70) and eighty (80) micrometers (m).

18. Semiconductor wafer, according to claim 1, characterized in that it further comprises an integrated circuit (IC) comprising the semiconductor layer and the BEOL interconnect structure; wherein the IC comprises a bulk device, in which the semiconductor layer comprises a bulk layer of semiconductor material.

19. Semiconductor wafer, according to claim 1, characterized in that it further comprises: an integrated circuit (IC) comprising a silicon-on-insulator (SOI) device comprising the semiconductor layer and the BEOL interconnect structure; wherein the semiconductor layer comprises a buried oxide layer (BOX) adjacent to the front side and a semiconductor substrate adjacent to the back side, such that the BOX layer is between the front side and the semiconductor substrate.

20. Semiconductor wafer, according to claim 1, characterized in that: the BEOL interconnect structure comprises a plurality of metal layers between the front side and the second side, each of the plurality of metal layers comprising one or more metal interconnects; and each of the first paths couples an antenna element from one or more antenna elements to one or more metal interconnects in a first metal layer among the plurality of metal layers; and further comprising: one or more second paths, each coupled to the RF circuit and each coupled to one or more metal interconnects in the first metal layer among the plurality of metal layers.

21. Semiconductor wafer, according to claim 1, characterized in that one or more first paths comprise one or more first paths through silicon (TSVs).

22. Semiconductor wafer, according to claim 1, characterized in that it is integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communication device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smartphone; a session initiation protocol (SiP) phone; a tablet; a phablet; a server; a computer; a laptop computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player;Petition 870250089186, dated 10 / 01 / 2025, page 151 / 180 6 / 9 digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.

23. Method for manufacturing a semiconductor wafer characterized in that it comprises: forming a semiconductor layer comprising: a first side; a back side opposite the first side; and a radio frequency (RF) circuit; forming a back-end line interconnect (BEOL) structure coupled to the RF circuit, wherein the BEOL interconnect structure comprises: a front side; and a second side opposite the front side, the second side coupled to the semiconductor layer; forming an antenna substrate adjacent to the back side of the semiconductor layer, comprising: forming one or more antenna layers, wherein a first antenna layer of the one or more antenna layers comprises one or more antenna elements; and forming one or more first paths, each coupling one antenna element of the one or more antenna elements to the BEOL interconnect structure to couple the one or more antenna elements to the RF circuit.

24. Method, according to claim 23, characterized in that the formation of one or more antenna layers comprises forming the first antenna layer comprising the formation of a metal layer that Petition 870250089186, dated 10 / 01 / 2025, page 152 / 180 7 / 9 comprises one or more metal structures comprising the one or more antenna elements in the first antenna layer.

25. Method according to claim 24, characterized in that the formation of the metal layer comprises forming a first redistribution layer (RDL).

26. A method according to claim 23, characterized in that it further comprises forming a dielectric material substrate adjacent to the back side of the semiconductor layer; and wherein the formation of the antenna substrate further comprises forming the antenna substrate on the dielectric material substrate.

27. A method according to claim 23, characterized in that it further comprises: forming a dielectric material substrate adjacent to the back side of the semiconductor layer; and forming a stripping stop layer on the dielectric material substrate; wherein the formation of the antenna substrate further comprises forming the antenna substrate adjacent to the stripping stop layer.

28. Method according to claim 26, characterized in that the formation of the dielectric material substrate further comprises: forming a silicon substrate adjacent to the back side of the semiconductor layer; and Petition 870250089186, dated 10 / 01 / 2025, p. 153 / 180 8 / 9 porosifying the silicon substrate to form a porous silicon substrate adjacent to the back side of the semiconductor layer.

29. Method according to claim 23, characterized in that the formation of the BEOL interconnect structure further comprises forming a plurality of metal layers between the front side and the second side, wherein the plurality of metal layers each comprises one or more metal interconnects; and further comprises forming one or more first ways in the antenna substrate and in the BEOL interconnect structure, each coupling an antenna element from the one or more antenna elements to one or more metal interconnects in a first metal layer among the plurality of metal layers.

30. A method according to claim 29, characterized in that it further comprises forming one or more secondary paths, each coupled to the RF circuit and each coupled to one or more metal interconnections in the first metal layer among the plurality of metal layers.

31. Method according to claim 29, characterized in that the formation of one or more first paths comprises forming one or more first paths through the silicon (TSVs) in the antenna substrate and in the BEOL interconnect structure, each coupling one antenna element of the one or more antenna elements to one or more metal interconnects in the first metal layer among the plurality of metal layers. Petition 870250089186, dated 10 / 01 / 2025, pp. 154 / 180 9 / 9 32. Method according to claim 26, characterized in that it further comprises grinding the dielectric material substrate to a first desired thickness to control a distance between one or more antenna elements and the RF circuit.

33. Method according to claim 26, characterized in that the formation of the semiconductor layer further comprises: forming a semiconductor substrate on the dielectric material substrate, wherein the semiconductor substrate comprises the back side; and forming a buried oxide layer (BOX) on the semiconductor substrate; wherein: forming the BEOL interconnect structure further comprises forming the BEOL interconnect structure adjacent to the BOX layer.

34. Method according to claim 26, characterized in that the formation of the semiconductor layer further comprises forming a silicon layer on the dielectric material substrate, wherein the silicon layer comprises the front side and the back side; and wherein: forming the BEOL interconnect structure further comprises forming the BEOL interconnect structure adjacent to the silicon layer. Petition 870250089186, dated 10 / 01 / 2025, pp. 155 / 180

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