Method, computer-readable non-transiential means, and apparatus

Description

1 / 63 “METHOD, COMPUTER-READABLE NON-TRANSIENTIAL MEANS, AND APPARATUS” CROSS-REFERENCE TO RELATED DEPOSIT REQUESTS

[0001] This patent application claims priority from pending non-provisional application US No. 18 / 300,137, filed April 13, 2023, and assigned to the assignee thereof, and expressly incorporated herein by reference as if fully presented below and for all applicable purposes. TECHNICAL FIELD

[0002] The aspects of the present disclosure relate generally to communication via a chip-to-chip connection and, in particular, to operation via a main band with a single clock range. BACKGROUND

[0003] As integrated circuit (IC) chips become smaller, it has become possible to package multiple chips into a single package. Each chip can be optimized for cost, materials, manufacturing process, and size, making it more suitable for a particular function. In such a package, a central processing unit (CPU) can be manufactured separately from a graphics processor, a special-purpose processor, volatile memory, non-volatile memory, an input / output controller, or other components. The different components can be packaged together to meet different needs without redesigning any of the individual components. By placing these disparate chips in a single package, the total system that includes the package can be smaller. Petition 870250089953, dated 02 / 10 / 2025, page 9 / 158 2 / 63 Similar principles apply to printed circuit board systems and subsystems. Furthermore, connections between disparate chips can be faster at a lower cost. In some cases, smaller chips, for example, a memory chip, a special-purpose processor, or an interface, are called chiplets; however, any chip can be called a chiplet.

[0004] The Universal Chiplet Interconnect Express (UCIe) specification, version 1.0 (UCIe 1.0), defines physical parameters and protocols for data transfer between a chip and a chiplet or between two chiplets. The connection can be direct or through a packet. The interconnection can be within a single package or through a circuit board between two different packages. UCIe 1.0 is intended to support interoperability between chiplets from different manufacturers and designers. The UCIe 1.0 interconnection includes a mainband which is the primary data transfer connection and a sideband which is the primary initialization and control connection. A sequence of state transitions is defined to take the interconnection from sideband initialization to mainband initialization to an active state and back to the standby and reset states.

[0005] A standard package version of UCIe 1.0 uses a main band with 16 data lanes and two clock lanes. The standard package version refers to a larger impact pitch connector, for example, 100 to 130 micrometers, and longer distances, for example, 10 to 25 mm, which can be found in order to connect two packages on a circuit board. An advanced package version of UCIe 1.0 Petition 870250089953, dated 02 / 10 / 2025, page 10 / 158 3 / 63 uses a main band with 64 data lanes, two clock lanes, and an extra redundant clock lane. The advanced package version refers to a smaller impact pitch connector, for example, 25 to 55 micrometers, and shorter distances, for example, less than 2 mm, which can be found in a package. New applications for each version and new versions may be developed over time. BRIEF SUMMARY

[0006] The following presents a summary of one or more implementations to provide a basic understanding of such implementations. This summary is not an extensive overview of all implementations considered and is not intended to identify key or critical elements thereof, nor to delineate the scope of any or all implementations. Its sole purpose is to present some concepts of one or more implementations in a simplified form as a prelude to the more detailed description that will be presented later.

[0007] In one example, a method includes sending a single-clock mode switching request from a first-chip module to a second-chip module partner via a sideband to request the enabling of a main-band single-clock mode of a chip-to-chip connection that connects the first chip module to the second chip module partner. A single-clock mode switching response is received from the module partner via the sideband to enable the single-clock mode, and data is communicated with the module partner via the mainband in single-clock mode using a clock. Petition 870250089953, dated 02 / 10 / 2025, page 11 / 158 4 / 63 functional.

[0008] In another example, a non-transient, computer-readable medium has instructions stored in it to cause a processor on an interconnection link to perform the operations of the method above.

[0009] In another example, an apparatus includes a first-chip module configured to provide a main band with a chip-to-chip connection from a second-chip module partner. A configuration register is configured to store main band parameters. A module processor is configured to send a single-clock mode switching request to a second-chip module partner via the sideband to request enabling of a main band single-clock mode and to receive a single-clock mode switching response from the module partner via the sideband to enable the single-clock mode. The processor is additionally configured to communicate data with the module partner via the main band in single-clock mode using the functional clock.

[0010] To accomplish the aforementioned and related purposes, one or more implementations include the attributes described fully in the present invention and particularly highlighted in the claims. The following description and the accompanying drawings set forth in detail certain illustrative aspects of one or more implementations. These aspects are indicative, however, of some of the various ways in which the principles of the various implementations can be employed, and the implementations Petition 870250089953, dated 02 / 10 / 2025, page 12 / 158 5 / 63 described are intended to include such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a block diagram of a module and a module partner coupled together by a chip-to-chip connection suitable for aspects of the present disclosure.

[0012] Figure 2 is a block diagram of a module and a module partner coupled together via a chip-to-chip connection and a faulty clock band in single-clock mode, according to aspects of the present disclosure.

[0013] Figure 3 is a block diagram of a module and a module partner coupled together by an alternative chip-to-chip connection suitable for aspects of the present disclosure.

[0014] Figure 4 is a block diagram of a module and a module partner coupled together via an alternate chip-to-chip connection and a faulty clock band in a single-clock mode, according to aspects of the present disclosure.

[0015] Figure 5 is a diagram of a connection-operated state machine, according to aspects of the present disclosure.

[0016] Figure 6 is a mainband initialization state machine diagram, according to aspects of the present disclosure.

[0017] Figure 7 is a message signaling diagram between a module and a module partner for switching to a single clock mode, according to aspects Petition 870250089953, dated 02 / 10 / 2025, page 13 / 158 6 / 63 of this publication.

[0018] Figure 8 is an alternative signaling diagram of messages between a module and a module partner for switching to a single clock mode, in accordance with aspects of the present disclosure.

[0019] Figure 9 is an alternative signaling diagram for additional messages between a module and a module partner to switch to a single clock mode, in accordance with aspects of the present disclosure.

[0020] Figure 10 is a block diagram of a pad with a module for a pad-to-pad connection, according to aspects of the present disclosure.

[0021] Figure 11 is a flow diagram of aspects for operating a chip-to-chip connection with a single clock mode, according to aspects of the present disclosure. DETAILED DESCRIPTION

[0022] The detailed description set forth below, together with the accompanying drawings, is intended to serve as a description of various configurations and is not intended to represent the only configurations in which the concepts described in the present invention can be practiced. The detailed description includes specific details in order to provide a complete understanding of various concepts. However, these concepts can be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0023] A pad-to-pad connection may refer, in the present invention, to a connection between any Petition 870250089953, dated 02 / 10 / 2025, p. 14 / 158 7 / 63 between two wafers, including a chip or a chiplet. A wafer can be considered as any integrated circuit that is formed and then cut, removed, or otherwise extracted from a wafer. The wafer can be silicon, glass, gallium nitride, or any other material suitable for forming integrated circuits. For wafer-to-wafer connection, each wafer includes a module. As in UCIe 1.0, a module includes a wafer-to-wafer adapter processor, physical logic (PHY), and PHY interface. The interface includes the transmitters and receivers for each line. A wafer can have multiple modules that can be coupled to modules from different wafers or to the same wafer. Although examples are presented in the context of UCIe 1.0, this interface specification is not necessary. The wafer-to-wafer connections described in the present invention can also be used to connect two packages via a printed circuit board.

[0024] In the examples of the present invention, chip-to-chip connections offer a bidirectional mainband with a high data rate using two clock lanes. As used in the present invention, one lane includes one line in each direction. 64 data lanes include 64 transmit data lines and 64 receive data lines. Each clock lane has one transmit clock line and one receive clock line. High data rates enabled by two or more clock lanes can consume power and generate heat, which is not necessary at all times. Instead of operating the mainband intermittently, an approach is described to allow the mainband to operate at a lower data rate, Petition 870250089953, dated 02 / 10 / 2025, page 15 / 158 8 / 63 for example, half the data rate with only one clock band in use. A single-clock mode can also be used in case one of the clock bands fails. The described approach can be applied to a UCIe mainband interconnect or to other mainbands between chips that have multiple clock bands. In the present description, a mainband is initialized using a sideband. Furthermore, parameters, configuration registers, signaling, and other attributes can be adapted to suit single-clock mode operation.

[0025] Figure 1 is a block diagram of a first chip 101 and a second chip 102 coupled together to a connection 100, as a chip-to-chip connection, for example, a standard UCIe packet interconnect, according to some aspects. Each chip may have many other components (not shown) to generate, process, store or communicate data or to supply or regulate power or perform operations, administration or management functions, etc., depending on the nature of the chip. The first chip 101 has a module 103 and the second chip 102 has a module partner 104. The module 103 and the module partner 104 may have the same structure or a different structure and may include additional components (not shown), including interfaces, adapters, logic, buffers, etc. The connection 100 has a mainband 130 and a sideband 136.

[0026] The main band 130 has a transmission portion 132 of module 103 and a reception portion 134 of module 103. The transmission portion 132 includes a data band with 16 transmission lines, a clock line P, Petition 870250089953, dated 02 / 10 / 2025, p. 16 / 158 9 / 63 a clock line N, a valid line, and a trace line. The valid line is used to frame the data on the data lines. The trace line can be used to perform runtime recalibration of the data lines and to repair a clock line. Module 103 has a mainband receiver 112 that is connected to a mainband 130 receiver 134. The receiver 134 includes a data band with 16 transmit lines, a clock line P, a clock line N, a valid line, and a trace line.

[0027] Sideband 136 also has a transmit and a receive portion, each with a sideband data line and a sideband clock line. Connection 100 is symmetrical in that module 103 has a mainband 110 transmitter and module partner 104 has a mainband 122 transmitter. These two transmitters perform the same functions and operations using the same protocols. Similarly, module 103 has a mainband 112 receiver and module partner 104 has a mainband 120 receiver. The present description refers to the module and its construction and operation, but the description applies equally to module partner 104 in the same way. Either side can initiate repair or training, and either side can initiate parameter and configuration changes, etc. Similarly, module 103 has a sideband 114 transmitter and a sideband 116 receiver.The 104 module partner also has a 124 sideband receiver and a 126 transmitter.

[0028] UCIe 1.0 has a layered protocol with Petition 870250089953, dated 02 / 10 / 2025, page 17 / 158 10 / 63 a physical layer and a wafer-to-wafer adapter in the module. The physical layer can consist of all types of current packaging options from different manufacturers and manufacturing processes. Examples include 2D packaging, 2.5D packaging, 3D packaging, and other approaches, for example, silicon bridge packages, embedded multi-die interconnect bridge (EMIB), chip-on-wafer-on-substrate (CoWoS) based on interposer and fan-out chip-on-substrate (FOCoS) interposer, and any other connection between two wafers on the same substrate or two packages on the same substrate. Optical or electrical connections can be made between the packages to other components. UCIe may be expanded in future revisions to connect wafers or packages through rack-based components.

[0029] UCIe 1.0 uses a protocol layer in the module that runs on top of the physical layer and has many attributes in common with Peripheral Component Interconnect Express (PCIe), Compute eXpress Link (CXL), and other pre-existing protocols. The PCIe protocol provides broad interoperability and flexibility. The CXL protocol provides low-latency, high-throughput connections. UCIe 1.0 may be expanded in future revisions to include other protocols and additional modifications beyond PCIe and CXL.

[0030] The structures and methods presented in the present invention are described in the context of UCIe 1.0, but may be adapted for future versions of UCIe under any Petition 870250089953, dated 02 / 10 / 2025, page 18 / 158 11 / 63 Name and other connection configurations with multiple clock bands. In Figure 1, the main band 130 has two clock bands operating at the same frequency with different phases. There is one P-clock line and one N-clock line in the transmit part of main band 132 and one P-clock line and one N-clock line in the receive part of main band 134. In UCIe 1.0, this is the main band connection. The two lines of the transmit clock band are called TCLKP and TCLKN, and the two lines of the receive clock band are sometimes called RCLKP and RCLKN. The transmit data band has 16 data lines in the transmit part 132, and the receive data band has 16 data lines in the receive part 134. According to UCIe 1.0, each clock band must be functional in each direction for data traffic to be carried in the main band of the connection. According to UCIe 1.0, a failure in any of the four clock lines renders the connection 100 unusable, making the effective bandwidth of the main band 130 zero, although the data lanes are functional.

[0031] Figure 2 is a block diagram of a first chip 201 and a second chip 202 coupled together to a connection 200, as a chip-to-chip 200 connection, for example, a standard UCIe 1.0 packet interconnect, according to some aspects. In this example, the N clock line has failed or been disabled in both directions and connection 200 is operating in a single clock mode. A module 203 of the first chip 201 has a mainband transmitter 210 which is connected to a mainband transmitter 232. The part Petition 870250089953, dated 02 / 10 / 2025, page 19 / 158 The 12 / 63 transmission portion 232 includes a data band with 16 transmission lines, one P-clock line, one N-clock line, one valid line, and one trace line. The transmission portion 232 is coupled to a mainband receiver 220 of a module partner 204 of the second 202 chip. Module 203 has a mainband receiver 212 that is connected to a mainband receiver portion 234 of the 230 mainband. The receiver portion 234 includes a data band with 16 transmission lines, one P-clock line, one N-clock line, one valid line, and one trace line. The receiver portion 234 is coupled to a mainband transmitter 222 of the module partner 204.

[0032] Module 203 also has a sideband transmitter 214 coupled, via sideband 236 of connection 200, to a sideband receiver 224 of module 204 partner. Module 203 has a sideband receiver 216 which is coupled, via sideband 236 of connection 200, to a sideband transmitter 226 of module 204 partner. The sideband has a sideband data line and a sideband clock line in each direction. In UCIe 1.0, the sideband has a clock band.

[0033] As shown, the mainband is operating without the N clock in the transmit section 232, sometimes called TCLKN, and without the N clock in the receive section 234, sometimes called RCLKN. However, using only the P clock in the transmit section 232, sometimes called TCLKP, and the P clock in the receive section 234, identified as RCLKP, the mainband 230 is capable of operating in a single-clock mode. Although the single-clock mode is shown as operating using only the clock Petition 870250089953, dated 02 / 10 / 2025, page 20 / 158 13 / 63 P, the N clock can be used instead. Single clock mode can be used in case of a failure of one of the clock lines or as a second mode with a lower data rate. A clock failure in the transmit, receive, or both lines can be detected during training or can occur during mainband operation. After detecting a clock failure, the module will be moved to a clock repair process to attempt to repair the clock. If this fails, then single clock mode can be used instead. Single clock mode operates with only one clock track so that single clock mode does not require both clocks to be functional. Single clock mode also provides lower speeds or data rates based on a clock that can be used during thermal control.

[0034] Figure 3 is a block diagram of a first chip 301 with a module 303 and a second chip 302 with a module partner 304 coupled together to a connection 300, for example, an advanced UCIe 1.0 packet interconnect, according to some aspects. Module 303 has a mainband transmitter 310 that is connected to a transmission portion 332 of a mainband 330. The transmission portion 332 includes a data band with 64 transmission lines, a P clock line, an N clock line, a valid line, and a trace line. The mainband transmission portion 332 also includes a redundant clock line (RD clock) and 4 redundant data lines (RD data). The redundant lines are configured for use when one or more of the primary data or clock lines fail. The portion of Petition 870250089953, dated 02 / 10 / 2025, page 21 / 158 14 / 63 transmission 332 is coupled to a mainband receiver 320 of module partner 304. Module 303 has a mainband receiver 312 which is connected to a mainband receiving portion 334 of the 330 mainband. The receiving portion 334 includes a data track with 64 transmission lines, one P clock line, one N clock line, one valid line, one trace line, one redundant clock line, and 4 redundant data lines. The receiving portion 334 is coupled to a mainband transmitter 322 of module partner 304.

[0035] A redundant clock band is provided in each direction as a repair mechanism in case of a failure in one of the clock bands. A failure in either clock band, P, N, will lead to the redundant clock band being configured to replace the faulty clock band. A failure in both clock bands in the transmit or receive direction cannot be repaired, and link training is interrupted. A failure in one of the clock bands and in the redundant clock band will result in the loss of the main 330 band, making the effective bandwidth zero, regardless of the functional data bands. This can occur, for example, due to an electrical short circuit between the clock bands. In this case, single-clock mode can be used as described below.

[0036] The module also has a sideband transmitter 314 coupled, via sideband 336 of connection 300, to a sideband receiver 324 of module partner 304. Sideband 336 may be the same as or similar to the sideband of the examples in Figures 1 and 2. Module 303 has a Petition 870250089953, dated 02 / 10 / 2025, page 22 / 158 15 / 63 sideband receiver 316 which is coupled, via sideband 336 of connection 300, to a sideband transmitter 326 of module partner 304. The sideband has a sideband data band and a sideband clock band together with a redundant sideband data band and a sideband clock band (not shown) in the transmit and receive directions.

[0037] Figure 4 is a block diagram of a first chip 401 with a module 403 and a second chip 402 with a module partner 404 coupled together to connection 400, for example, an advanced UCIe 1.0 packet interconnect, according to some aspects. In this example, the N clock band and the redundant clock band have both failed or been disabled in both directions, and connection 400 is operating in a single clock mode. Module 403 has a mainband transmitter 410 that is connected to a transmit part 432 of a mainband 430. The transmit part 432 includes a data band with 64 transmit lines, a P clock line, an N clock line, a redundant RD clock line, a valid line, a trace line, and 4 redundant RD data lines. The 432 transmission section is coupled to a 420 mainband receiver from module partner 404.Module 403 has a mainband receiver 412 that is connected to a mainband 430 receiver section 434. The receiver section 434 includes a data track with 64 transmit lines, one P clock line, one N clock line, one redundant RD clock line, one valid line, one trace line, and 4 redundant RD data lines. The receiver section 434 is coupled to a... Petition 870250089953, dated 02 / 10 / 2025, page 23 / 158 16 / 63 main band transmitter 422 of the 404 module partner.

[0038] Module 403 also has a sideband transmitter 414 coupled, via sideband 436 of connection 400, to a sideband receiver 424 of module 404 partner. Module 403 has a sideband receiver 416 which is coupled, via sideband 436 of connection 400, to a sideband transmitter 426 of module 404 partner. The sideband has a sideband data line and a sideband clock line in each direction.

[0039] As shown, the mainband is operating without the N clock in the transmit part 432, the redundant clock in the transmit part 432, the N clock in the receive part 434, and the redundant clock in the receive part 434. In UCIe 1.0, the same would be described as the mainband operating without TCLKN, TCLKR, RCLKN, and RCLKR, which is not allowed in UCIe 1.0. However, using only the P clock in the transmit part 432 and the P clock in the receive part 434, the mainband 430 is able to operate in a single-clock mode. Although the single-clock mode is shown as operating with the P clock, alternatively, the N clock or the RD clock can be used instead. As in the standard packet, the single-clock mode can be used in the event of a clock band failure or as a second mode with a lower data rate.

[0040] Figure 5 is a state machine diagram of a 500 state machine for operating a chip-to-chip connection, according to some aspects. The state machine is related to a link layer form. Petition 870250089953, dated 02 / 10 / 2025, page 24 / 158 17 / 63 of the physical layer of a 200, 400 connection described above. The state machine can be implemented in a module or elsewhere on the chip that controls the chip-to-chip connection. The same state machine can be used for standard mode or advanced UCIe mode, or other configurations with adaptations to accommodate differences in ranges, as described above. The 500 state machine starts with a 502 reset state which can be obtained upon startup or after recovery from a deep sleep or low power state, for example, L2 state 514, or to recover from a fault. The 502 reset state can also be entered by command from higher-level layers of the chip, for example, a command to switch to single-clock mode.

[0041] Starting from reset state 502, the state machine enters a sideband initialization state 504. The sideband is a low-speed, high-reliability part of the connection. It is configured to be easily initialized even when there are other faults or harsh environmental conditions. After the sideband initialization state 504, the state machine can advance to a mainband initialization state 506. The mainband initialization state includes a clock selection substate 520. A single-clock mode, selected in the clock selection substate 520, can be initialized in the mainband initialization state 506 using a mainband initialization (MBINIT) that invokes the single-clock mode.

[0042] After band initialization state Petition 870250089953, dated 02 / 10 / 2025, page 25 / 158 Once main band 506 is completed, including clock selection substate 520, state machine 500 advances from main band initialization state 506 to main band training state 508. In main band training state 508, main band data bands are being trained. After main band training state 508, state machine 500 advances to link initialization state 510. Link initialization state 510 refers to all connections between the module and the module partner. After link initialization state 510, the state machine moves to an active state 512 for data communication between the module and the module partner. The state machine remains in active state 512 until some event requires a transition.

[0043] One type of transition is to a PHY 516 retraining state. The PHY 516 retraining state allows the PHY layer (physical layer) of the connection to be retrained in case of errors or changes in the circumstances or conditions of the connection. After the PHY 516 retraining state, the state machine returns to the mainband training state 508 and then to the link initialization state 510 and back to the active state 512 that was recovered from the PHY 516 retraining state.

[0044] Another type of transition is to an L1 / L2 514 state. The L1 / L2 514 state includes two different low-power or standby conditions to accommodate inactivity in the pad-to-pad connection. To reduce power consumption, heat generation, and / or wear on the pads or connecting components, the 500 state machine can transition to an L1 standby mode that disables Petition 870250089953, dated 02 / 10 / 2025, p. 26 / 158 19 / 63 many of the connection components, especially through the mainband part. From the L1 standby mode of the L1 / L2 state 514, the state machine 500 transitions to the mainband training state 508. From the mainband training state 508, the state machine transitions to the link initialization state 510 and back to the active state 512. The L2 standby mode is a deeper standby mode with more components, including clocks, turned off to save more power. Starting from the L2 standby mode, the state machine 500 transitions from the L1 / L2 state 514 back to the reset state 502. From the reset state 502, the complete state machine transition process is performed to achieve the active state 512. There may be more or fewer standby or low-power states than the L1 standby and L2 standby states to suit different implementations.

[0045] An additional state is a training error state 518 reached as a transition from the reset state 502. This state is a deadlock and results in an inoperable connection. If the module is restarted, then the module will be re-entered into the reset state 502 and may be able to initialize or may return to the training error state 518.

[0046] With the use of state machine 500, single clock mode is entered or terminated using clock selection substate 520. Clock selection substate 520 can be entered as part of mainband initialization state 506. When the clock configuration of the mainband part of the connection is changed, due to a Petition 870250089953, dated 02 / 10 / 2025, page 27 / 158 20 / 63 higher layer command or upon detection of a clock fault, the mainband is initialized to the new clock configuration in the mainband initialization state 506. The mainband is then trained to the new clock configuration in the mainband training state 508. After the mainband training state, 508, the state machine 500 transitions to the link initialization state 510 and to the active state 512.

[0047] The 520 clock selection substate is entered from the 502 reset state. Under some circumstances, the chip-to-chip connection is initiating, and the connection may be initialized through all states using single-clock mode selection or another clock mode selection as the state machine progresses through the mainband initialization state. Under some circumstances, a fault is detected in one or more clock lines, in which case the state machine returns to the 502 reset state to determine the fault in the clock lines and to initialize the connection using one or more functional clocks. Under some circumstances, a higher layer of the module or chip commands a transition to or from single-clock mode due to traffic, performance, thermal conditions, or other conditions.State machine 500 can transition through L2 standby mode in L1 / L2 state 514 back to reset state 502.

[0048] Figure 6 is a mainband 600 initialization state machine that provides additional details about the mainband initialization state. Petition 870250089953, dated 02 / 10 / 2025, page 28 / 158 21 / 63 506, according to some aspects. The mainband initialization state machine 600 is entered by the mainband initialization state into a parameter state 602 during which the parameters for chip-to-chip connection operation are shared between the module and the module partner. Then, the clock selection state 604 includes selecting single or multiple clocks and selecting which clock lines, for example, P, N, and / or RD, will be used for the active state. The clock selection state 604 also includes configuration parameters in configuration registers to support the selected modes. After the clock selection state 604, a calibration state 606 is entered to calibrate the links to use the selected clock and data bands.

[0049] Repair clock state 608 follows calibration state 606 and allows training patterns to be sent and received between the module and the module partner to test the clock connections between the module and the module partner through the connection. Repair clock state 608 is where a clock fault is detected and where the functional clock lines are determined.

[0050] The valid repair state 610 is used to train the valid range that is used to frame the data on the data lines. The valid range is a type of clock signal. In UCIe 1.0, the valid signal marks the beginning and middle of a data packet on the data lines. For each 8-bit data packet with 8 unit intervals (UIs), the valid signal is asserted for the first 4 UIs and de-asserted for the second 4 UIs. It is asserted again at the beginning of the next 8-bit packet. Petition 870250089953, dated 02 / 10 / 2025, page 29 / 158 22 / 63

[0051] The main band reversal state 612 allows a main band test to determine if reversal should be applied to the main band data tracks. With reversal, track 16 or track 64 becomes track 1 and the track designation counts up to track 1 which becomes track 16 or track 64.

[0052] The mainband repair state 614 is a mainband data communication training state in which known patterns are transmitted on the data bands to test each data band for proper operation. This is similar to the clock repair process described in the context of Figure 7, but for the data bands.

[0053] After completing the operations of the main band initialization state machine 600, the link training state machine then transitions out of the main band initialization state 506 to the main band training state 508, as shown in Figure 5.

[0054] Figure 7 is a signaling diagram 700 of messages between a module 702 and a module partner 704 to switch to single-clock mode in the event of a clock failure, according to some aspects. Signaling begins after sideband initialization has been performed. The module and module partner send sideband initialization messages 712. This corresponds to the end of the sideband initialization state 504 of Figure 5. The shorter arrow is used to indicate that signaling is through the sideband. Module 702 then sends a sideband initialization parameter request. Petition 870250089953, dated 02 / 10 / 2025, page 30 / 158 23 / 63 main 714 to module partner 704. Module partner 704 responds with a mainband initialization parameter response 716. These are also exchanged via the initialized sideband. Module 702 and module partner 704 perform this handshake procedure to determine if a single clock mode is supported.

[0055] UCIe 1.0 provides a more specific example of a parameter exchange. There is an exchange called MBINIT.PARAM, and the parameters to enable single-clock mode can be exchanged during this exchange or during a different operation. In UCIe 1.0, for both standard and advanced packages, the mainband initialization request message is called MBINIT.PARAM configuration req. This is a request to exchange parameters with the UCIe module partner. The module partner's response is called MBINIT.PARAM configuration resp and is also a sideband message. When single-clock mode is used, one or more parameters can be exchanged in the same sideband messages. A first parameter is a single-clock mode support parameter to indicate that the sender of the parameter supports single-clock mode. A second parameter is a single-clock enable parameter to request that single-clock mode be enabled.A third parameter is a functional clock parameter to indicate the clock range to be used for single-clock mode.

[0056] In one aspect, this parameter can be called the SCM support parameter or the single clock mode support parameter. The single clock mode (SCM) support parameter can be in Petition 870250089953, dated 02 / 10 / 2025, page 31 / 158 24 / 63 is a one-bit value that indicates whether the requesting module supports SCM or does not support SCM. If the module partner also supports SCM, then it can set a parameter in a configuration register to indicate that the module supports SCM. In one aspect, the parameter is set to 1b in the module partner's response message. In some aspects, the module and module partner are pre-configured to support single-clock mode, and there is no SCM support handshake procedure during mainband initialization.

[0057] An administrator, implementer, manufacturer, supplier, local or remote controller, or other entity may select that the chip-to-chip connection is permitted to operate in single-clock mode. In some respects, this is accomplished by setting a parameter in a mainband configuration register, for example, a clock configuration register to allow single-clock mode operation. The parameter may be added to a UCIe 1.0 register called MainBand CLK_config_reg. Alternatively, a different configuration register may be used. During the mainband parameter initialization phase, which includes the mainband initialization parameter request 714 and the mainband initialization parameter response 716, module 702 and module partner 704 perform the handshake procedure across the sideband to determine whether single-clock mode is supported on both the module and the module partner.If single-clock mode is supported on both the 702 module and the 704 module partner, then another configuration parameter can be stored in a register that... Petition 870250089953, dated 02 / 10 / 2025, page 32 / 158 25 / 63 identifies which clock range will be used in single-clock mode for both transmit and receive directions. This corresponds to identifying a functional clock for single-clock mode. In the example in Figure 2, P and N are available. In the example in Figure 4, P, N, and RD are available. After this configuration, the identified clock range is set for subsequent link training.

[0058] After mainband initialization, the process can then proceed to mainband training and link the initialization to an active state with mainband data communication. However, in the example in Figure 7, a clock fault is detected in module 702, which causes a clock repair process 706. A repair clock initialization request 718 is sent from module 702 to module partner 704 using the sideband. The module partner responds with a repair clock initialization response 720. This prepares the connection for the repair clock training pattern 722. The repair clock training pattern 722 is bidirectional across the mainband and follows a known pattern so that the transmitter and receiver at each end are able to detect and train the clock signal. A longer arrow is used to indicate that the repair clock training pattern 722 is across the mainband.The 706 clock repair process allows for the detection of any clock fault, repairing a detected clock fault by training the receiver on the current clock signal and clock line, and detecting functional clock lines. Petition 870250089953, dated 02 / 10 / 2025, p. 33 / 158 26 / 63

[0059] After the 722 clock repair training pattern has been transmitted over the mainband to both clocks and in both directions, module 702 will send a 724 clock repair result request, and module partner 704 will send a 726 clock repair result response. This concludes the clock repair process. The module receives, in the 726 clock repair result response, a list of clock faults and functional clock lines. The module partner can then store the results of the 706 clock repair process in a configuration register. Similarly, the module partner can send a request (not shown) to the module and receive a response about the clock repair training pattern, which is stored in the configuration register on the module partner. In another aspect, module 702 maintains the configuration register. In some aspects, parameters are sent to the module partner from the module.

[0060] The UCIe 1.0 clock repair process, called MBINIT.REPAIRCLK, is a more specific variation of the 706 clock repair process described above. In some instances, the UCIe 1.0 clock repair process can be used in the process shown in Figure 7. The clock and trace bands are checked for functional operation at the lowest data rate. The clock repair training pattern has a sequence that begins when the UCIe module sends the MBINIT.REPAIRCLK init req sideband message and waits for a response. When the UCIe module partner is ready to receive the clock training pattern in RCKP_L, RCKN_L, RTRK_L, then the module partner Petition 870250089953, dated 02 / 10 / 2025, page 34 / 158 UCIe module 27 / 63 responds with a sideband response MBINIT.REPAIRCLK init resp. After receiving the MBINIT.REPAIRCLK init resp sideband message, the UCIe module sends 128 iterations of the clock repair pattern (currently defined as 16 clock cycles followed by 8 lower cycles) in TCKP_L, TCKN_L, TTRK_L on the main band. The training pattern exercises both P and N clocks so that any fault can be detected at either clock.

[0061] The UCIe module partner detects clock repair in RCKP_L, RCKN_L, and RTRK_L in the main band. Detection is considered successful if at least 16 consecutive cycles of the clock repair pattern are detected. The UCIe module partner logs the detection result for RCKP_L, RCKN_L, and RTRK_L. The module receiver and the UCIe module partner receiver each generate a result in response to the clock repair training pattern. The UCIe module sends an MBINIT.REPAIRCLK result req message in the sideband and receives an MBINIT.REPAIRCLK result resp sideband response message with the recorded result of the clock repair training pattern for all three main band signals, RCKP_L, RCKN_L, and RTRK_L.

[0062] When, as a result of the 706 clock repair process, a clock fault is detected, instead of aborting all data communication, the module may switch to single-clock mode. The clock repair training pattern tests both mainband clock tracks so that the module receiver and the module partner receiver each know which of the clock tracks is functional, if any. If the clock test applies to only one track Petition 870250089953, dated 02 / 10 / 2025, page 35 / 158 28 / 63 clock, then training can continue to determine if another clock band is functional. When another clock band is functional, then the functional clock band can be used for subsequent link training and data transfer in single-clock mode with only one functional mainband clock. In the case of a faulty clock band, the module transmitter and the corresponding module partner transmitter can turn off the faulty clock band and also put the corresponding transmission lines into a triple state. The transmitter is sending a clock on the functional transmission clock line and putting any transmission clock line other than the functional transmission clock line into a triple state.Similarly, the corresponding receivers on the module and module partner can also be disabled for the faulty clock bands, so that any receiving clock line other than the functional receiving clock line is disabled. The action of putting the lines into a triple state prevents any received signal from interfering with the other clock signals. Any well-known triple state condition can be used, for example, a high impedance coupled to the line so that it can be pulled down or up by the external connection.

[0063] Alternatively, even if no clock fault is detected, an application can still enable single-clock mode using either of the two functional clocks. With both clocks functional, the clock configured in the clock configuration register, CLK_config_reg, will be used for subsequent link training and data transfer. If there is only one Petition 870250089953, dated 02 / 10 / 2025, page 36 / 158 29 / 63 functional clock, so this clock can be stored in a configuration register after the clock repair process. Using the functional clock request, the module communicates the selected clock with the module partner using this sideband message.

[0064] To switch to single-clock mode, in some instances, module 702 sends a single-clock mode switching request 728 to the module partner. This is sent over the sideband while the mainband is still being initialized, as shown in Figure 7. The single-clock mode switching request is then answered with a response, single-clock mode switching response 730, from module partner 704. If there is no such response and only one of the clock bands is functional, the mainband will not function. The response from module partner 704 can be used to indicate that module partner 704 has enabled a single-clock mode (SCM). The single-clock mode switching request 728 and the single-clock mode switching response 730 may include a single-clock mode enable parameter.The single-clock mode enable parameter can be stored in a configuration register on the module or in another register on the first chip.

[0065] In some respects, the functional clock or the standard clock for single-clock mode has already been identified. In some respects, the functional clock can be identified as part of the 728 single-clock mode switching request. In some respects, the clock to be used for single-clock mode can be identified with band signaling. Petition 870250089953, dated 02 / 10 / 2025, page 37 / 158 30 / 63 additional sideband. In the example in Figure 7, there is a functional clock request 732 that includes information about which clock is selected for use in single-clock mode. The functional clock request 732 may include a functional clock parameter to identify a functional clock for single-clock mode. The functional clock parameter may be sent in response to receiving the clock repair result response 726, which indicates which clocks are faulty. Upon receiving a functional clock request sideband message 732, the module partner 704 updates its appropriate configuration register with the identified functional clock and then responds with a functional clock response sideband message 734.

[0066] After successfully switching to the SCM using the selected clock band, the process is closed with a final handshake procedure via the sideband. Module 702 sends a clock repair request made 736 and the partner module 704 responds with a clock repair response made 738.

[0067] Upon completion of the switch to SCM, the status can then change to a valid repair state. This is followed by mainband training 708 via the mainband and then mainband data communication 710 via the mainband in single-clock mode. In this state of the mainband initialization process of Figure 7, the mainband has been switched to a lower data rate or has been rescued from a clock fault that would otherwise be fatal, depending on the circumstances. In another aspect, if, in UCIe 1.0, a Petition 870250089953, dated 02 / 10 / 2025, page 38 / 158 31 / 63 Module partner does not support SCM or if more than one clock band fault is detected between RCKP_L, RCKN_L and RTRK_L, then the module and module partner will not be able to operate on the mainband connection and may switch to a training error state after performing a training error handshake procedure on the sideband.

[0068] Table 1 is an example of a clock configuration register, called CLK_config_reg in the present invention, which can be configured to support single-clock mode for a mainband with only two clocks, P and N, for example, a mainband for the standard packet. More registers can be added to accommodate more clocks and other connection configurations. In some respects, the value in each position is set to zero by default and after initialization. During mainband initialization, described above, a fault in either of the two receive lines is set to 1 in the RxClk_Fault position. A fault in either of the two transmit clock lines is set to 1 in the TxClk_Fault position. Either of these faults renders the mainband inoperable in a two-clock mode. Rx_ClkP, Rx_ClkN, Tx_ClkP, and Tx_ClkN indicate which clocks have a fault, based on the clock repair training pattern.Additionally, an SCM_support position is set to 1 to indicate that the transmitter and receiver in the main band support SCM. An SCM_enable position is set to 1 to indicate that the transmitter and receiver have enabled and are operating in SCM. A functional_clock position can indicate whether the N or P clock band is identified as the functional clock in SCM. Petition 870250089953, dated 02 / 10 / 2025, page 39 / 158 32 / 63 Table 1 RSVD RxClk_fault Rx_ClkP Rx_ClkN RSVD TxClk_fault Tx_Clk_P Tx_ClkN SCM_support SCM_enable functional_clock

[0069] When the SCM_support bit is set or is 1, then the main band can be operated even if one of the clock lines has a fault, as indicated in the clock configuration register. When the SCM_enable bit is set or is 1, the main band will be operating with a functional clock. The clock selection substate described above allows the functional clock line to be selected for the active state. The configuration of the clock lines and the selection of the functional clock can be determined using a clock selection table in which the configuration of the active clock bands is stored.

[0070] Table 2 is a clock selection table configured to enable the determination of the active clock selection for a main band with two clock ranges, P and N. Table 2 can be expanded to accommodate more clock ranges as needed. Table 1 and Table 2 are examples of information that can be stored in the configuration and parameter registers. The ClkP, ClkN, and Clk_fault bits represent the clock configured for use in the standard packet context. For the advanced packet context, an additional redundant clock can be specified. Table 2 can be used to determine whether the default active state can be used under no-fault conditions or to determine which clock should be active for an SCM active state. The module can use the result from the table and Petition 870250089953, dated 02 / 10 / 2025, page 40 / 158 33 / 63 send the result as a functional clock parameter with the module's functional clock request 732. In the examples, the module and the module partner maintain a clock selection table, such as Table 2, and independently determine the same clock line for SCM. Table 2 Tx / Rx Clk_fault ClkN ClkP Clock selection 0 1 1 Both tracks are active (default state) 0 0 1 ClkP is active for SCM 0 1 0 ClkN is active for SCM 1 0 1 ClkN is faulty, ClkP is active in SCM 1 1 0 ClkP is faulty, ClkN is active in SCM 1 0 0 Both tracks are active (training error state)

[0071] Figure 8 is a signaling diagram 800 of messages between a module 802 and a module partner 804 to describe a switch to single-clock mode for any type of connection in which the mainband has two or more clocks, for example, an N clock, a P clock, and a redundant clock (RD) in the UCIe 1.0 advanced package. The signaling begins with the sideband initialization performed 812. This corresponds to the end of the sideband initialization state 504 in Figure 5. The module 802 then sends a mainband initialization parameter request 814 to the module partner. The module partner responds with a mainband initialization parameter response 816. After this handshake procedure, the SCM enable value for the appropriate configuration register is set or not set, and the initialization Petition 870250089953, dated 02 / 10 / 2025, page 41 / 158 34 / 63 proceeds to an 806 clock repair process that includes an 822 clock repair training pattern.

[0072] After the main band initialization parameter request 814 and the main band initialization parameter response 816, the clock repair process 806 is initiated in response to a clock fault detected in module 802. In some cases, the clock repair process results in a repair using the clock repair process 806, and the module returns to main band data communication 810 using both clock bands or using the redundant clock band. In the clock repair process, a repair clock initialization request 818 is sent from module 802 to the module partner 804 using the sideband. The module partner responds with a repair clock initialization response 820. This prepares the connection for the repair clock training pattern 822.The 822 clock repair training pattern is transmitted over the mainband and follows a known pattern so that the transmitter and receiver at each end are able to detect and train the clock signal. The 822 clock repair training pattern in the mainband includes patterns for the P, N, and RD clocks.

[0073] After the clock repair training pattern 822 has been transmitted over the mainband to all clocks, module 802 will then send a clock repair result request 824, and module partner 804 will send a clock repair result response 826. This completes the clock repair process. The module partner can then store the results of Petition 870250089953, dated 02 / 10 / 2025, page 42 / 158 35 / 63 Clock repair process 806 in the configuration register. A similar process can be performed in which the Clock repair training pattern 822 is sent by the module partner and the module sends a Clock repair result response (not shown) to the module partner. Parameter exchange can be used to populate Table 2.

[0074] The UCIe 1.0 clock repair process for advanced packet is a more specific example of the 806 clock repair process. In the UCIe 1.0 advanced packet process, each clock, track, and redundant physical clock strip (TCKP_P / RCKP_P, TCKN_P / RCKN_P, TTRK_P / RTRK_P, and TCKRD_P / RCKRD_P) is independently checked to detect possible electrical openings or short circuits between the two clock pins. Single-ended clock receivers or an independent detection mechanism is used to determine any faults in any of the clock strips by checking each line. The UCIe module and the UCIe module partner enable transmitters and receivers on the clock, track, and redundant clock strips. All other data transmitters and receivers can remain in a triple state.

[0075] The UCIe module sends the MBINIT.REPAIRCLK init req sideband message and awaits a response. The UCIe module partner, when ready to receive the clock training patterns in RCKP_L, RCKN_L, RTRK_L, RCKRD_L, responds with MBINIT.REPAIRCLK init resp. In the context of advanced packetization, each clock band is trained separately. Consequently, the UCIe module sends 128 iterations of the clock repair training pattern (16 clock cycles, followed by 8 lower cycles) only in Petition 870250089953, dated 02 / 10 / 2025, page 43 / 158 36 / 63 of its TCKP_P. The other clock tracks (TCKN_P, TTRK_L, and TCKRD_L) are placed in a triple state. This clock repair training pattern is then repeated for the other tracks, while the inactive tracks are placed in a triple state until all four tracks, TCKP_P, TCKN, TTRK_P, and TCKRD_P, have been tested and trained. The UCIe module partner detects this pattern in RCKP_L, RCKN_L, RTRK_L, and RCKRD_L, respectively. Detection is successful if at least 16 consecutive iterations of the clock repair pattern are detected. The UCIe module partner logs the detection result for RCKP_L, RCKN_L, RTRK_L, and RCKRD_L. After completing the pattern transmission, the UCIe module sends MBINIT.REPAIRCLK result req as a sideband message to obtain the recorded result and awaits a response. The UCIe module partner responds with the MBINIT sideband message.REPAIRCLK result resp with a write result for RCKP_L, RCKN_L, RTRK_L and RCKRD_L.

[0076] For each clock repair training pattern, the training pattern must be correctly detected only on the corresponding receive line and not on any other receive lines. For example, if detection is successful simultaneously on any two or more of RCKP_L, RCKN_L, RTRK_L, and RRDCK_L, then an electrical short circuit is implied. If detection is unsuccessful on any of RCKP_L, RCKN_L, RTRK_L, and RRDCK_L, then repair will be required on the physical range TCKP_P / RCKP_P.

[0077] When a fault is detected in only one range (CKP or CKN or TRK), then in the advanced packet of Petition 870250089953, dated 02 / 10 / 2025, page 44 / 158 37 / 63 The UCIe module will be able to apply a repair to its clock transmitter or band using the redundant clock band, RD. The UCIe module sends a sideband message MBINIT.REPAIRCLK apply repair req with the repair information. This information indicates which faulty clock band should be replaced by the redundant clock band. The UCIe module partner applies the repair to the faulty band (CKP or CKN or TRK) and sends a sideband message MBINIT.REPAIRCLK apply repair resp confirming the repair.

[0078] When a fault is detected in more than one track (CKP, CKN, and TRK), then the mainband connection can no longer operate at full speed with two clocks. In other words, if the mainband clock / track tracks cannot be repaired because repair is required in two of the RCKP_L, RCKN_L, and RRDCK_L tracks, or if an electrical short circuit is detected, then the UCIe interconnect cannot be repaired for standard operation in a two-clock mode. Without SCM, the UCIe module and the UCIe module partner must switch to the training error state after performing a training error handshake procedure.

[0079] Any functional clock band can be used to operate mainband 810 data communication in single-clock mode. If at least one of the clock bands, the P, N, or redundant (RD) bands, is not defective, then the 802 module can enable a single-clock mode (SCM) by sending a message: a single-clock switching request 828 via the sideband. The single-clock switching request 828 can include Petition 870250089953, dated 02 / 10 / 2025, page 45 / 158 38 / 63 is an SCM enablement parameter that is stored in a configuration register. The module partner enables SCM on its receiver and transmitter and responds with an acknowledgment message via the sideband, shown as a single-clock mode switching request 830. In some respects, the single-clock mode switching request 828 also includes a functional clock identification for use in single-clock mode.

[0080] Upon receiving the response, module 802 sends a message through the sideband to indicate the functional clock to be used with the SCM using a functional clock request 832. The indicated functional clock can be any of the functional clocks. If only one clock is functional, then this request and response are not necessary. The functional clock can be selected using the information indicated in the clock selection table, Table 2. As an example, if CLKP is faulty, then CLKN will be selected, and vice versa. The partner module 804 selects and updates the clock range in its own configuration register, for example, CLK_config_reg, Table 1, based on the functional clock request sideband message 832 and sends a functional clock response message 834 through the sideband.Then, the module sends a clock repair sideband message made 836 and the module partner responds with a clock repair sideband response made 838. In response to the clock repair response made 838, the module can then switch to the valid repair state 610, as shown in the state diagram of Figure 6. Initialization continues further with the signaling of... Petition 870250089953, dated 02 / 10 / 2025, page 46 / 158 39 / 63 main band training 808 in the main band training state 508 of Figure 5 and then for main band data communication 810 in an active state 512, as shown in the state diagram of Figure 5, to operate the main band in single clock mode. The module transmitter can be placed in a triple state and turned off for the faulty clock bands, and the module partner can disable the receiver for the faulty clock band. A similar approach can be used for the module partner transmitter and the module receiver.

[0081] If the main band clock / track tracks cannot be repaired even with the use of SCM because there is no available single clock / track track that is not faulty, then the chip-to-chip connection has failed. Repair is required on more than two tracks RCKP_L, RCKN_L and RRDCK_L. The UCIe module and the UCIe module partner switch to a training error state after performing a training error handshake procedure.

[0082] Figure 9 is a signaling diagram 900 of messages between a module 902 and a module partner 904 to switch to single clock mode with no clock miss. This can be done to reduce power, reduce data rate, or for other benefits. Signaling begins after sideband initialization has been performed. The module and module partner have already initialized mainband data communication 906. In this example, module 902 and module partner 904 have already performed a parameter handshake procedure to determine if SCM is supported. Petition 870250089953, dated 02 / 10 / 2025, page 47 / 158 40 / 63

[0083] A local or remote controller or other entity determines that the chip-to-chip connection should switch to single-clock mode. In response to this determination or command, module 902 sends a single-clock mode switching request 928 to the module partner. This is a request to enable SCM. It is sent over the sideband when mainband data communication 906 is still active. The single-clock mode switching request is then answered with a single-clock switching response 930 from module partner 904. SCM is now enabled. If there is no such response, then mainband data communication 906 may continue.

[0084] The functional clock or the standard clock for single-clock mode is optionally identified with a functional clock request 932 from module 902 and a functional clock response 934 from the module partner. In some instances, the functional clock has already been identified in a previous exchange or was identified in the single-clock mode switching request 928. Module 902 and module partner 904 update the appropriate configuration register, and the process is closed with a clock repair request 936 from the module to the module partner and a clock repair response 938 from module partner 904 to module 902. In some instances, the functional clock request 932 and the functional clock response 934 are sent before or during mainband data communication 906. In some instances, there is no functional clock request 932 or functional clock response 934 because a functional clock parameter has already been provided by the module. Petition 870250089953, dated 02 / 10 / 2025, page 48 / 158 41 / 63 902. The previously provided functional clock parameter can be used to determine the functional clock for SCM. The process continues with optional mainband training 908 using the new SCM and then mainband data communication 910 on the SCM. In some examples, mainband training was originally performed for mainband data communication 906 and there is no need to repeat mainband training 908 so that this operation is not performed.

[0085] Figure 10 is a block diagram of an example of a hardware implementation for a 1000 chip, for example, a central processor, a graphics processor, a special-purpose processor, volatile memory, non-volatile memory, an input / output controller, or any other suitable component with a 1010 chip-to-chip connection. In this example, the chip has 1020 processors to perform the chip's primary operations and a 1005 memory. The chip has a 1014 module to support a 1010 chip-to-chip connection with a 1004 chip-to-chip adapter processor, a 1006 computer-readable medium, a 1012 logic PHY, a 1016 receive block, and a 1018 transmit block. The 1004 chip-to-chip adapter processor performs the operations described above to fulfill the 1010 chip-to-chip connection between the chip 1000 and one or more other tablets (not shown).

[0086] According to various aspects of disclosure, an element, or any portion of an element, or any combination of elements, can be implemented with module 1014. Examples of module 1014 include Petition 870250089953, dated 02 / 10 / 2025, p. 49 / 158 42 / 63 microprocessors, microcontrollers, digital signal processors (DSPs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gate logic, discrete hardware circuits and other suitable hardware configured to control the 1010 chip connection and clocking modes, as described throughout this disclosure. In several examples, the 1000 chip can be configured to perform any one or more of the functions described in the present invention. The chip contains other components (not shown) configured to perform other functions of the chip, as is appropriate for the type of chip.

[0087] In this example, the 1000 chip can be implemented with a bus architecture, generally represented by the 1002 bus. The 1002 bus can include any number of interconnect buses and bridges, depending on the specific application of the 1014 module, the 1000 chip, and general design constraints. The 1002 bus communicatively couples various circuits, including 1020 processors, the chip-to-chip adapter processor 1004, the 1005 memory, and the computer-readable media (generally represented by the 1006 computer-readable media) that have instructions stored on them. The 1002 bus can also connect various other circuits, such as timing sources, peripherals, data buffers, modules, power management circuits, and other processing cores, which are not described further below. An interface of Petition 870250089953, dated 02 / 10 / 2025, page 50 / 158 The 43 / 63 bus 1008 provides an interface between the bus 1002 and other optional external interfaces, for example, a control interface 1030 and a data interface 1032, etc. The 1020 processors are a higher layer relative to the 1004 chip-to-chip adapter processor and are coupled to the chip-to-chip adapter processor via the bus 1002. The 1020 processors can communicate operations, administration, or management control with the 1004 chip-to-chip adapter processor, or the 1004 chip-to-chip adapter processor can operate autonomously. In some examples, the chip-to-chip adapter receives a request to reduce a data rate from the mainband of a higher layer, for example, the 1020 processors.

[0088] The 1030 control interface can be used to provide a communication interface or means of communication from various other devices and appliances (e.g., other devices housed in the same package or system) via an internal bus or external transmission medium, as a command and control interface for power regulation, activation testing, and other purposes. The 1032 data interface can be used to provide data connections other than the 1010 chip-to-chip connection to other types of components in the package or system. The 1030 control interface and the 1032 data interface can be connected to a higher layer to receive reset and configuration commands that can cause the chip-to-chip processor to switch to a single-clock mode.

[0089] Module 1014 includes a receiving block Petition 870250089953, dated 02 / 10 / 2025, page 51 / 158 44 / 63 PHY 1016 corresponds to the sideband and mainband receivers described above, and a transmission block PHY 1018 corresponds to the sideband and mainband transmitters described above. The transmission block PHY 1016 and the reception block PHY 1018 are coupled to the chip-to-chip connection 1010, which corresponds to the physical part of the sideband 136 and mainband 130 tracks described above, which couple the first chip 101 and the second chip 102 through pins on their respective chip connectors. The module also includes logic PHY 1012, which may include the link logic to control the data applied to each line and the state machines described above under the control of the chip-to-chip adapter processor. The logic PHY 1012 may also include clock generators coupled to clock sources to generate the sideband and mainband clock signals, as described above.

[0090] The chip-to-chip adapter processor 1004 is responsible for managing the PHY logic 1012 and interface processing, including the execution of software stored on the computer-readable medium 1006. The software, when executed by the chip-to-chip adapter processor 1004, causes the module 1014 to perform the various functions described below for any particular device. The computer-readable medium 1006 and memory 1005 can also be used to store data that is manipulated by the chip-to-chip adapter processor 1004 during software execution.

[0091] The 1004 chip adapter processor may be a part of the 1020 processors or Petition 870250089953, dated 02 / 10 / 2025, page 52 / 158 45 / 63 of one or more of the other processor cores of the 1000 chip (not shown) and perform operations by means of a processor core executing software stored on computer-readable media 1006, or the chip-to-chip adapter processor 1004 may be independent of any other processing resources of the 1000 chip to execute software stored on computer-readable media 1006 using its own processing resources. The term software shall be interpreted broadly to mean instructions, instruction sets, code, code segments, program code, programs, subprograms, software chips, applications, software applications, software packages, routines, subroutines, objects, executable elements, execution threads, procedures, functions, etc., whether they are referred to as software, firmware, middleware, microcode, hardware description language or otherwise.The software can reside on a computer-readable medium 1006. The chip-to-chip adapter processor 1004 controls the operations performed by state machines, for example, those in Figures 5 and 6, and causes the signaling of the signaling diagrams 700, 800, 900, and causes the clock repair training patterns to be transmitted and received.

[0092] Computer-readable media 1006 may be non-transient computer-readable media. Non-transient computer-readable media include, by way of example, a magnetic storage device, a flash memory device, random access memory (RAM), and read-only memory. Petition 870250089953, dated 02 / 10 / 2025, page 53 / 158 46 / 63 (ROM - read only memory), a programmable ROM (PROM - programmable read only memory), an erasable PROM (EPROM - erasable read only memory), an electrically erasable PROM (EEPROM - electrically erasable read only memory), a register, and any other suitable means for storing software and / or instructions that can be accessed and read by a controller. The computer-readable medium 1006 may reside in module 1014 or elsewhere in the 1000 chip. The computer-readable medium 1006 may be incorporated into firmware for the operation of a state machine or parameters of an application-specific integrated circuit (ASIC). Those skilled in the art will recognize the best ways to implement the described functionalities presented throughout this disclosure, depending on the particular application and the general design constraints imposed on the overall system.

[0093] The 1000 chip can be configured to perform any one or more of the operations described in the present invention. In some aspects of the disclosure, the chip-to-chip adapter processor 1004, as used in the 1000 chip, may include a set of circuits configured for various functions.

[0094] The chip adapter processor 1004 is coupled to memory 1005 via bus 1022. Memory 1005 includes parameter and configuration registers 1015 which may include parameters for different clock operating modes and the status of the clock and data tracks, as shown in Table 1 and Table 2. Any other parameters and configuration values ​​may also be stored, including those Petition 870250089953, dated 02 / 10 / 2025, page 54 / 158 47 / 63 for mainband operation in PCIe or CXL operation.

[0095] The 1004 chip adapter processor may include a 1041 single-clock mode configuration circuitry for sending requests and receiving responses with a chip partner to enable a single-clock mode and for setting an enable parameter in a clock configuration register of the parameter and configuration registers 1015. The 1041 single-clock mode configuration circuitry may include one or more hardware components that provide the physical structure that performs various processes related to sending requests and receiving responses from a chip partner to enable a single-clock mode and setting an enable parameter. The 1041 single-clock mode configuration circuitry may include functionality for a means of sending and a means of receiving messages to enable a single-clock mode and means of setting an enable parameter in a clock configuration register.The single-clock-mode configuration circuitry 1041 can be further configured to execute single-clock-mode configuration instructions 1051 included in the computer-readable medium 1006 to implement the single-clock-mode configuration described in the present invention.

[0096] The 1004 chip adapter processor may include a set of 1042 single-clock-mode switching circuits configured to send and receive single-clock-mode switching messages and determine when to switch to single-clock mode, Petition 870250089953, dated 02 / 10 / 2025, page 55 / 158 48 / 63 as discussed in the present invention. The single-clock-mode switching circuitry 1042 may include functionality for a command-responsive medium or table inference from, for example, Table 2 to switch to single-clock mode and for sending and receiving messages to switch to single-clock mode. The single-clock-mode switching circuitry may additionally define parameters for operating in single-clock mode in a clock configuration register. The single-clock-mode switching circuitry 1042 may be additionally configured to execute single-clock-mode switching instructions 1052 included in the computer-readable medium 1006 to implement one or more functions described in the present invention.

[0097] The 1014 chip adapter processor of module 1004 may include a set of single-clock-mode functional clock ID circuits 1043 configured to perform operations of selecting a functional clock and sending and receiving sideband messages about the selected functional clock for single-clock mode, as discussed in the present invention. The single-clock-mode functional clock ID circuit set 1043 may include functionality for sending a request and receiving a response with the chip partner via the sideband that identifies a functional clock for single-clock mode. The single-clock-mode functional clock ID circuit set 1043 may include functionality for a means of selecting a functional clock and means of sending and receiving messages about the Petition 870250089953, dated 02 / 10 / 2025, page 56 / 158 49 / 63 functional clock selected for single clock mode via the sideband. The single clock mode functional clock ID circuit set 1043 can be further configured to execute single clock mode functional clock ID instructions 1053 included in the computer-readable medium 1006 to implement one or more functions described in the present invention.

[0098] The chip-to-chip adapter processor 1004 may include a data communication circuitry 1044 configured to communicate data with another chip via a main band of the chip-to-chip connection 1010 using the functional clock in single-clock mode, as discussed in the present invention. The data communication circuitry 1044 may include functionality for a means of communicating data with another chip via a main band using the functional clock in single-clock mode. The data communication circuitry 1044 may additionally define parameters for operating in single-clock mode in a clock configuration register. The data communication circuitry 1044 may be additionally configured to execute data communication instructions 1054 included in the computer-readable medium 1006 to implement one or more functions described in the present invention.

[0099] The circuit architecture described in the present invention can be implemented in one or more ICs, chips, chiplets, wafers, interposers, packages, system printed circuit boards (PCBs), etc. The circuit architecture described in the present invention Petition 870250089953, dated 02 / 10 / 2025, page 57 / 158 50 / 63 can also be manufactured using various process technologies, such as complementary metal-oxide semiconductor (CMOS), N-channel metal-oxide semiconductor (NMOS), P-channel metal-oxide semiconductor (PMOS), bipolar junction transistor (BJT), bipolar CMOS (BiCMOS), silicon-germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.

[0100] Figure 11 is a process flow diagram illustrating an example of a method for using a single clock mode with a main band of a chip-to-chip connection, such as the connections in Figures 1 to 4. The method can be implemented in the chip-to-chip adapter processor 1004 of Figure 10, or in another set of circuits and software, as described in the context of Figure 10. The method 1100 can begin in block 1108 with the sending of a single clock mode (SCM) switching request from a module of a first chip to a module partner of a second chip via the sideband to request the enabling of a single clock mode of a main band of a chip-to-chip connection connecting the first chip module to the second chip module partner.

[0101] The method can be started after detection Petition 870250089953, dated 02 / 10 / 2025, page 58 / 158 51 / 63 of a clock fault during data communication in a multi-clock mode. The method can be initiated after detecting a clock fault during a clock training pattern of a mainband initialization. The method can be initiated in response to a request from a higher layer. The method can be initiated on mainband initialization due to a configuration register status.

[0102] In response to the request message, the module partner may send a response. Method 1100 continues in block 1110 with the reception of a single-clock mode switching response from the module partner via the sideband to enable single-clock mode. This can be performed during mainband initialization or after mainband data communication has already been established. Some examples may include storing a single-clock mode enablement parameter in a configuration register in response to receiving the single-clock mode switching response via the sideband.

[0103] In block 1112, in response to receiving the response, a functional clock request is sent to the module partner via the sideband that identifies a functional clock for single-clock mode. This is an optional operation. In some respects, the functional clock was previously identified or the functional clock is identified in the switching request to SCM of block 1108. In block 1114, the module partner may optionally send an additional response so that a functional clock response is received from Petition 870250089953, dated 02 / 10 / 2025, page 59 / 158 52 / 63 module partner via sideband. This can be performed during mainband initialization or after mainband data communication has already been established.

[0104] After single clock mode is enabled, the functional clock is identified, and switching to single clock mode is performed using the identified functional clock, mainband communication can be performed. In block 1116, data communication with the module partner is performed via the mainband in single clock mode using the functional clock. In single clock mode, the module can put any transmit clock line other than the functional clock into a triple state and disable any receive clock line other than the functional clock.

[0105] In some instances, the first chip module and the second chip module partner are configured for single-clock mode support before any initialization or have already been configured due to a previous initialization. In some instances, single-clock mode support is determined before single-clock mode is enabled. To determine single-clock mode support in block 1102, sending a single-clock mode support request to the module partner via the sideband is optionally performed to indicate that the module supports single-clock mode.

[0106] The module partner received the request and sends a response. In block 1104, the reception of a single clock mode support response via the sideband is optionally performed to indicate that the partner Petition 870250089953, dated 02 / 10 / 2025, page 60 / 158 Module 53 / 63 supports single-clock mode. Block 1106 refers to storing a single-clock mode support parameter in a configuration register. This can be done by the module in response to the sideband single-clock mode support response.

[0107] As used in the present invention, or is intended to be interpreted in an inclusive sense, except where explicitly stated otherwise. For example, a or b may include only a, only b, or a combination of a and b. As used in the present invention, a phrase referring to at least one of or one or more of a list of items refers to any combination of those items, including single members. For example, at least one of: a, b, or c is intended to cover the examples of: only a, only b, only c, a combination of a and b, a combination of a and c, a combination of b and c, a combination of a and b and c.

[0108] The various illustrative components, logic, logic blocks, modules, circuits, operations, and algorithm processes described in connection with the implementations disclosed in the present invention can be implemented as electronic hardware, firmware, software, or combinations of hardware, firmware, or software, including the structures disclosed in this descriptive report and their structural equivalents. The interchangeability of hardware, firmware, and software has been described, in general terms, in terms of functionality, and illustrated in the various illustrative components, blocks, modules, circuits, and processes described above. Whether such functionality is implemented in hardware, firmware, or software depends on Petition 870250089953, dated 02 / 10 / 2025, page 61 / 158 54 / 63 particular application and design limitations imposed on the system as a whole.

[0109] The various logic blocks, modules, and illustrative circuits described in connection with the exemplary aspects disclosed in the present invention can be implemented or realized with a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described in the present invention. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any conventional processor, controller, microcontroller, or state machine.A processor can also be implemented as a combination of computing devices, for example a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors together with a DSP core, or any other such configuration.

[0110] In one or more exemplary aspects, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored or transmitted in the form of one or more instructions or code stored on a computer-readable medium. Computer-readable media include both computer storage media and communication media, including Petition 870250089953, dated 02 / 10 / 2025, page 62 / 158 55 / 63 Any means that facilitates the transfer of a computer program from one place to another. Storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM, or other optical disk storage devices or magnetic disk storage, or any other media that can be used to carry or store the desired program code in the form of instructions or data structures and that can be accessed by a computer. Combinations of the above should also be included within the scope of computer-readable media.

[0111] The following section provides an overview of examples from this disclosure.

[0112] Example 1: A method comprising sending a single-clock mode switching request from a module of a first chip to a module partner of a second chip via a sideband to request the enabling of a single-clock mode of a mainband of a chip-to-chip connection that connects the first chip module to the second chip module partner; receiving a single-clock mode switching response from the module partner via the sideband to enable the single-clock mode; and communicating data with the module partner via the mainband in single-clock mode using a functional clock.

[0113] Example 2: The method from example 1, where the sending of the switching request to single clock mode is performed during a mainband initialization.

[0114] Example 3: The method from example 1 or 2 that Petition 870250089953, dated 02 / 10 / 2025, page 63 / 158 56 / 63 additionally includes disabling any main band clock other than the functional clock.

[0115] Example 4: The method of example 3 which additionally comprises placing, in a triple state, any transmission clock line other than the functional clock.

[0116] Example 5: The method of any one or more of the above examples which additionally comprises receiving a request to reduce a data rate from the mainband of a higher layer and sending the request to switch to single-clock mode to the module partner being performed in response to the request to reduce the data rate.

[0117] Example 6: The method of any one or more of the above examples, wherein the communication of data in single clock mode comprises communicating data in single clock mode at half the data rate of the communication of data with multiple clock bands.

[0118] Example 7: The method of any one or more of the above examples which additionally comprises storing a single-clock mode enable parameter in a configuration register in response to receiving the single-clock mode switch response.

[0119] Example 8: The method of any one or more of the above examples which additionally comprises, before sending the single-clock mode switching request: sending a single-clock mode support request to the module partner via the sideband to indicate that the module supports single-clock mode; and receiving a single-clock mode support response via the sideband. Petition 870250089953, dated 02 / 10 / 2025, page 64 / 158 57 / 63 on the side to indicate that the module partner supports single clock mode.

[0120] Example 9: The method from example 8 which additionally comprises storing a single clock mode support parameter in a configuration register.

[0121] Example 10: The method of any one or more of the above examples which additionally comprises, before sending the switching request to single clock mode: initializing a mainband with the module partner using a multi-clock mode; communicating data with the module partner via the mainband in multi-clock mode; and detecting a clock fault during data communication in multi-clock mode.

[0122] Example 11: The method of any one or more of the above examples which additionally comprises: sending a functional clock request to the module partner via the sideband that identifies a functional clock for single clock mode; and receiving a functional clock response from the module partner via the sideband.

[0123] Example 12: The method from example 11, where sending the functional clock request involves sending the functional clock request during a mainband initialization.

[0124] Example 13: The method of example 11 which additionally comprises, after the detection of the clock fault: sending a clock repair training pattern; receiving a clock repair result response; and determining the functional clock, wherein the sending of the functional clock request is performed in response to the receipt of the clock repair result response. Petition 870250089953, dated 02 / 10 / 2025, page 65 / 158 58 / 63

[0125] Example 14: The method from example 13, where sending the clock repair training pattern involves sending iterations of a clock repair pattern to the module partner on each mainband clock line.

[0126] Example 15: A non-transient, computer-readable medium that has instructions stored therein for making a processor or chip perform operations comprising: sending a single-clock mode switching request from a module of a first chip to a module partner of a second chip via a sideband to request the enabling of a single-clock mode of a mainband of a chip-chip connection that connects the first chip module to the second chip module partner; receiving a single-clock mode switching response from the module partner via the sideband to enable the single-clock mode; and communicating data with the module partner via the mainband in single-clock mode using a functional clock.

[0127] Example 16: The middle of example 15, wherein the operations additionally comprise receiving a request to reduce a data rate from the mainband of a higher layer and sending the sideband switching request to single clock mode to the module partner is performed in response to the request to reduce the data rate.

[0128] Example 17: The middle of example 15 or 16, where single-clock mode data communication comprises communicating single-clock mode data at half the rate. Petition 870250089953, dated 02 / 10 / 2025, page 66 / 158 59 / 63 data communication with multiple clock bands.

[0129] Example 18: The means of any one or more of examples 15 to 17, wherein the operations additionally comprise, before sending the single-clock mode switching request: sending a single-clock mode support request to the module partner via the sideband to indicate that the module supports single-clock mode; and receiving a single-clock mode support response via the sideband to indicate that the module partner supports single-clock mode.

[0130] Example 19: The means of any one or more of Examples 15 to 18, wherein the operations additionally comprise, before sending the switching request to single clock mode: initializing a mainband with the module partner using a multi-clock mode; communicating data with the module partner via the mainband in multi-clock mode; and detecting a clock fault during data communication in multi-clock mode.

[0131] Example 20: The method of example 19, in which the operations additionally comprise, after the detection of the clock fault: sending a clock repair training pattern; receiving a clock repair result response; and determining the functional clock, in which the sending of the functional clock request is performed in response to the reception of the clock repair result response.

[0132] Example 21: An apparatus comprising: a first-pad module configured to provide a main band with a pad-to-pad connection of a Petition 870250089953, dated 02 / 10 / 2025, page 67 / 158 A 60 / 63 module partner from a second chip; a configuration register configured to store mainband parameters; and a module processor configured to: send a sideband switching request for single-clock mode from the module to the module partner to request the enabling of a mainband single-clock mode; receive a sideband switching response for single-clock mode from the module partner to enable the single-clock mode; send a sideband functional clock request to the module partner that identifies a functional clock for the single-clock mode; receive a sideband functional clock response from the module partner; and communicate data with the module partner via the mainband in single-clock mode using the functional clock.

[0133] Example 22: The device from example 21, where the module processor is additionally intended to disable any mainband clock other than the functional clock.

[0134] Example 23: The device of example 21 or 22, in which the module processor is additionally intended to put into triple state any transmission clock line other than the functional clock.

[0135] Example 24: The apparatus of any one or more of examples 21 to 23, wherein the module processor is additionally intended to store a single-clock mode enable parameter in the configuration register in response to the sideband switching response for single-clock mode.

[0136] Example 25: An apparatus comprising Petition 870250089953, dated 02 / 10 / 2025, page 68 / 158 61 / 63 means to send a sideband parameter configuration request to a module partner to enable a single clock mode with a main band of a chip-to-chip connection; means to receive a sideband parameter configuration response from the module partner to enable the single clock mode with the main band; means to set an enable parameter in a clock configuration register to enable the single clock mode; means to send a sideband request to the module partner to switch to single clock mode; means to receive a sideband response from the module partner to switch to single clock mode; means to send a sideband request to the module partner that identifies a functional clock for the single clock mode; means to receive a sideband response from the module partner that identifies the functional clock for the single clock mode;and means to communicate data with the module partner via the main band using the functional clock in single-clock mode.

[0137] It should be noted that the present disclosure is not limited to the illustrative terms used above to describe aspects of the present disclosure. For example, the chip-to-chip connection may also be called an interconnection, a bus, a link, or another term.

[0138] Although aspects of this disclosure are discussed above using the example of UCIe 1.0, it should be considered that this disclosure is not limited to that example and can be used with other standards. Petition 870250089953, dated 02 / 10 / 2025, page 69 / 158 62 / 63

[0139] Any reference to an element in the present invention using a designation, for example, first, second, and so forth, does not generally limit the quantity or order of those elements. Instead, these designations are used in the present invention as a convenient way to distinguish between two or more elements or instances of an element. Thus, a reference to the first and second elements does not mean that only two elements can be employed, or that the first element must precede the second element.

[0140] In the present disclosure, the word exemplifier is used to mean serving as an example, an instance, or an illustration. Any implementations or aspects described in the present invention as exemplifiers should not necessarily be interpreted as preferential or advantageous in relation to other aspects of the disclosure. Similarly, the term aspects does not require that all aspects of the disclosure include the attribute, advantage, or mode of operation discussed. The term coupled is used in the present invention to refer to electrical coupling or other type of communication, direct or indirect, between two structures. Furthermore, the term approximately means within ten percent of the stated value.

[0141] The preceding description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined in the present invention can be applied to other variations without departing from the Petition 870250089953, dated 02 / 10 / 2025, p. 70 / 158 63 / 63 spirit or scope of disclosure. Thus, the disclosure is not intended to be limited to the examples described in the present invention, but rather to be in accordance with the broader scope consistent with the innovative principles and attributes disclosed in the present invention. Petition 870250089953, dated 02 / 10 / 2025, p. 71 / 158

Claims

1 / 7 CLAIMS 1. A method characterized by comprising: sending a single-clock mode switching request from a module of a first chip to a module partner of a second chip via a sideband to request the enabling of a single-clock mode of a mainband of a chip-chip connection that connects the first chip module to the second chip module partner; receiving a single-clock mode switching response from the module partner via the sideband to enable the single-clock mode; and communicating data with the module partner via the mainband in single-clock mode using a functional clock.

2. A method according to claim 1, characterized in that the sending of the switching request to single-clock mode is performed during a mainband initialization.

3. Method according to claim 1, characterized by further comprising disabling any mainband clock other than the functional clock.

4. Method according to claim 3, characterized by further comprising placing, in a triple state, any transmission clock line other than the functional clock.

5. Method, according to claim 1, characterized by further comprising receiving a Petition 870250089953, dated 02 / 10 / 2025, page 136 / 158 2 / 7 request to reduce a data rate of the mainband of a higher layer and sending the switching request to single clock mode to the module partner being performed in response to the request to reduce the data rate.

6. Method, according to claim 1, characterized by the single-clock mode data communication comprising communicating data in single-clock mode at a data rate that is half the data rate of data communication with multiple clock bands.

7. A method according to claim 1, characterized by further comprising storing a single-clock mode enable parameter in a configuration register in response to receiving the single-clock mode switching response.

8. Method according to claim 1, characterized by further comprising, before sending the single-clock mode switching request: sending a single-clock mode support request to the module partner via the sideband to indicate that the module supports single-clock mode; and receiving a single-clock mode support response via the sideband to indicate that the module partner supports single-clock mode.

9. A method according to claim 8, characterized by further comprising storing a single clock mode support parameter in a configuration register.

10. Method according to claim 1, Petition 870250089953, dated 10 / 02 / 2025, pp. 137 / 158 3 / 7 characterized by further comprising, before sending the switching request to single clock mode: initializing a mainband with the module partner using a multi-clock mode; communicating data with the module partner via the mainband in multi-clock mode; and detecting a clock fault during data communication in multi-clock mode.

11. A method according to claim 1, characterized by further comprising: sending a functional clock request to the module partner via the sideband that identifies the functional clock for single-clock mode; and receiving a functional clock response from the module partner via the sideband.

12. Method, according to claim 11, characterized in that sending the functional clock request comprises sending the functional clock request during a mainband initialization.

13. Method according to claim 10, characterized by further comprising, after detection of the clock fault: sending a clock repair training pattern; receiving a clock repair result response; and determining the functional clock, wherein the sending of the functional clock request is performed in response to receiving the clock repair result response. Petition 870250089953, dated 10 / 02 / 2025, pp. 138 / 158 4 / 7 14. Method, according to claim 13, characterized in that the sending of the clock repair training pattern comprises sending iterations of a clock repair pattern to the module partner on each mainband clock line.

15. A non-transient, computer-readable medium characterized by having instructions stored therein to cause a chip processor to perform operations comprising: sending a single-clock mode switching request from a module of a first chip to a module partner of a second chip via a sideband to request the enabling of a single-clock mode of a mainband of a chip-chip connection that connects the first chip module to the second chip module partner; receiving a single-clock mode switching response from the module partner via the sideband to enable the single-clock mode; and communicating data with the module partner via the mainband in single-clock mode using a functional clock.

16. Means according to claim 15, characterized in that the operations further comprise receiving a request to reduce a data rate from the mainband of a higher layer and sending the single-clock mode switching request to the module partner in response to the request to reduce the data rate. Petition 870250089953, dated 10 / 02 / 2025, pp. 139 / 158 5 / 7 17. Means according to claim 15, characterized in that the data communication in single clock mode comprises communicating data in single clock mode at a data rate that is half the data rate of data communication with multiple clock bands.

18. Means according to claim 15, characterized in that the operations further comprise, before sending the single-clock mode switching request: sending a single-clock mode support request to the module partner via the sideband to indicate that the module supports single-clock mode; and receiving a single-clock mode support response via the sideband to indicate that the module partner supports single-clock mode.

19. Means according to claim 15, characterized in that the operations further comprise, before sending the switching request to single clock mode: initializing a mainband with the module partner using a multi-clock mode; communicating data with the module partner via the mainband in multi-clock mode; and detecting a clock fault during data communication in multi-clock mode.

20. Means according to claim 19, characterized in that the operations further comprise, after detection of the clock fault: sending a clock repair training pattern; receiving a clock repair result response; and determining the functional clock, wherein the sending of the functional clock request is performed in response to receiving the clock repair result response.

21. Apparatus characterized by comprising: a first-chip module configured to provide a main band with a chip-to-chip connection to a second-chip module partner; a configuration register configured to store main band parameters; and a module processor configured to: send a single-clock mode switching request from the module to the module partner via the sideband to request the enabling of a single-clock mode of the main band; receive a single-clock mode switching response from the module partner via the sideband to enable the single-clock mode; and communicate data with the module partner via the main band in single-clock mode using a functional clock.

22. Device according to claim 20, characterized in that the module processor is additionally intended to disable any mainband clock other than the functional clock.

23. Device, according to claim 20, characterized in that the module processor is intended to additionally place, in a triple state, any transmission clock line other than the functional clock.

24. Device according to claim 21, characterized in that the module processor is additionally intended to store a single-clock mode enable parameter in the configuration register in response to the single-clock mode switching response. Petition 870250089953, dated 10 / 02 / 2025, pp. 142 / 158

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