Synchronous enabled type condition presetting CMOS trigger

Abstract

This invention relates to simultaneous CMOS trigger in D trigger technique field, which is characterized by the following: it is composed of simultaneous circuit and first and second locking connection, wherein, the circuit comprises two CMOS transmission gates for inputting data signal and one output signal of the second locker and the two gates outputs the data signals to the first locker under the control of the anti-phase signals. The first locker adopts input data controlled pre-charging circuit and the second locker adopts two same circuits parameter single phase clock, wherein, the output end is symmetric to the down end with one circuit of output end of the two locker to realize the stability of the clock signal in low level.

Description

technical field [0001] The presented circuit is part of the series "Conditional Precharged CMOS Flip-Flops". It is characterized by "synchronous scanning" control. The technical field of direct application is the design of low-power flip-flop circuits. Background technique [0002] With the advancement of CMOS integrated circuit manufacturing technology, the scale and complexity of integrated circuits are increasing day by day, and the power consumption and heat dissipation of integrated circuits have been paid more and more attention from industry and academia. Based on the current integrated circuit design style, in large-scale digital circuit systems, the energy consumed by the clock network accounts for a high proportion of the total energy consumption of the entire circuit; among them, in the working state of the circuit, the energy consumed in the clock interconnection network and timing The energy of the circuit unit (flip-flop: Flip-Flop) has become an important sou...

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Problems solved by technology

However, the problem with the SAFF_CP circuit is that since the output latch circuit adopts a cross-coupled NAND2 (NAND2: two-input NAND gate) structure, the delay of the rising edge and falling edge of the output of the flip-flop circuit will be extremely different. Symmetry, which poses potential problems for the use of circuit cells

It can be seen that for the SAFF_CP circuit that uses a cross-coupled NAND2 latch circuit as the output terminal, the output terminal signal will always have a delay of one gate more than the rising edge inversion when the falling edge of the output signal occurs, thus causing the rising edge delay of the circuit and The problem of asymmetrical falling edge delay

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