Method of manufacturing nonvolatile memory
A non-volatile, manufacturing method technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as the inability to increase the integration of components, the large size of the programmable read-only memory storage unit, and reduce manufacturing costs , The process method is simple, the effect of reducing the manufacturing cost
Inactive Publication Date: 2008-09-10
POWERCHIP SEMICON CORP
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[0005] However, the above-mentioned SONOS device with a split gate structure has a larger memory cell size because the split gate structure requires a larger split gate area, so its memory cell size is smaller than that of the electrically erasable device with stacked gates. Moreover, the size of the storage unit of the programmable read-only memory is large, and there is a problem that the integration degree of the components cannot be increased.
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[0055]1A-1F are cross-sectional views of the manufacturing process of a non-volatile memory according to an embodiment of the present invention. First, referring to FIG. 1A , a substrate 100 is provided. The substrate 100 is, for example, a silicon substrate. The substrate 100 can at least be divided into a memory cell area 102 and a peripheral circuit area 104 . Next, a plurality of memory cells 106 are formed on the substrate 100 in the memory cell region 102 . The memory cell 106 is composed of a composite layer 108 , a gate 110 , and a cap layer 114 . The formation method of the memory cell 106 is, for example, to form a patterned photoresist layer (not shown) on the memory cell region 102 after sequentially forming a composite dielectric material layer, a conductive layer, and an insulating material layer on the substrate 100 , and then perform an etching process to pattern the above-mentioned material layer in the memory cell region 102, and remove the above-mentioned m...
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The method for fabricating non-volatile memory includes steps: forming multiple first memory units on substrate of memory region; the first memory unit includes first lamination layer, first grid electrode, and top cover layer, and there is a gap between adjacent two first memory units; then, multiple grid electrodes are formed in these gaps; these gaps and second lamination layer constitute second memory units; these second memory units and these first memory units constitute a row of memory units. In the method, grid structure in region of periphery circuits is formed in same time. Grid electrodes in gaps and grid electrodes in region of periphery circuits are formed from same conductor layer.
Description
technical field [0001] The invention relates to a method for manufacturing a memory, in particular to a method for manufacturing a non-volatile memory. Background technique [0002] Among all kinds of non-volatile memory products, it has the advantages of multiple data storage, reading, erasing, etc., and the stored data will not disappear after power off. Programmable read-only memory (EEPROM) has become a memory element widely used in personal computers and electronic equipment. [0003] In US Pat. No. 4,939,690, a flash memory structure is proposed, in which a floating gate and a control gate are made of doped polysilicon. Moreover, in order to avoid the problem of misjudgment of data due to excessive erasure phenomenon during erasing of the flash memory structure. A select gate is additionally provided on the sidewalls of the control gate, the floating gate, and the substrate to form a split-gate structure. [0004] In addition, in the prior art, a charge trapping lay...
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IPC IPC(8): H01L21/8238H01L21/8247
Inventor 曾维中魏鸿基毕嘉慧
Owner POWERCHIP SEMICON CORP