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Chip capsulation structure, and fabricating method

A technology of chip packaging structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve the problems of complex packaging process, complex process and high damage rate

Inactive Publication Date: 2008-11-26
GIOTEK OPTOELECTRONICS +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In order to make thinner and lighter substrates, the packaging process must be more complicated to produce products that meet the requirements. Due to the complexity of the process, there will be doubts about the high damage rate

Method used

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  • Chip capsulation structure, and fabricating method
  • Chip capsulation structure, and fabricating method
  • Chip capsulation structure, and fabricating method

Examples

Experimental program
Comparison scheme
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Embodiment Construction

[0013] The following is a preferred embodiment to illustrate the chip packaging structure and manufacturing method of the present invention. Figure 1 to Figure 12 Shown is a structural cross-sectional view of each step of the chip packaging structure and its manufacturing method according to a preferred embodiment of the present invention.

[0014] Please refer to FIG. 1 , first, a carrier board 10 is provided, and an insulating layer 20 and a conductive layer 30 are disposed on the carrier board 10 on the insulating layer 20 . In one embodiment, the insulating layer 20 and the conductive layer 30 can be integrally formed commercially available structures, such as RCC resin / copper foil board (RCC resin / copper). In another embodiment, it can be divided into three steps. First, the insulating layer 20, such as a glass fiber prepreg cloth, is made of an existing appropriate method such as pasting, printing, spin coating, spraying or pressing. , set on the carrier 10, such as a ...

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PUM

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Abstract

The invention is capable of connecting different metal layers electrically instead of connecting same metal layer in traditional method. Being different from method of coating layer for preventing soldering, the disclosed method fills protection layer on metal layer directly, and coats chip and electric connection structure. Moreover, using carrier plate as support can produce more light weighted and thinner basal plate. The disclosed method is feasible to current technique in packaging industry without need of adding additional equipment and procedure. Advantages are: reducing flow of printed circuit board, and lowering packaging cost.

Description

technical field [0001] The present invention relates to a chip packaging technology, in particular to a chip packaging structure for making a thin double-sided substrate (substrate) and a manufacturing method thereof. Background technique [0002] In view of the rapid improvement of semiconductor technology with the functions of products such as computers and network communications, it is necessary to meet the needs of diversification, portability, and miniaturization, so that the chip packaging industry will break away from traditional technologies and move towards high-power, high-density, light, and thin The development of high-precision manufacturing processes such as miniaturization. In order to make thinner and lighter substrates, the packaging process must be more complicated to produce products that meet the requirements. Due to the complexity of the process, there may be concerns about high damage rates. Contents of the invention [0003] In view of this, the pre...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/60H01L21/56H01L23/488H01L23/31
CPCH01L24/97H01L2224/48091H01L2924/00014
Inventor 庄永富
Owner GIOTEK OPTOELECTRONICS