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Semiconductor encapsulation structure and its making method

A packaging structure and semiconductor technology, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve the problem of being unable to configure passive components to improve the electrical function of the packaging structure, so as to improve the electrical function and Quality, increase the effect of electrical function

Inactive Publication Date: 2008-12-24
SILICONWARE PRECISION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] In addition, the above-mentioned various packaging structures cannot be equipped with passive components to improve the electrical function of the packaging structure

Method used

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  • Semiconductor encapsulation structure and its making method
  • Semiconductor encapsulation structure and its making method
  • Semiconductor encapsulation structure and its making method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0035] see Figure 5A to Figure 5E , which shows a schematic cross-sectional view of Embodiment 1 of the semiconductor package structure of the present invention and its manufacturing method.

[0036] Embodiment 1 of the present invention is mainly described in a batch manner, so as to improve the process efficiency and enable mass production. Of course, it can also be performed in a single wafer manner, but is not limited thereto.

[0037] like Figure 5A As shown, it provides a substrate module sheet 54A with a plurality of substrates 54, and each of the substrates 54 is formed with at least one opening 541. The form of the opening 541 is corresponding to the active surface of the semiconductor chip to be packaged subsequently. The layout arrangement of the pads. In this embodiment, the bonding pads on the active surface of the semiconductor chip to be packaged are arranged in an I-shape, and correspondingly, the openings 541 on the substrate 54 are also correspondingly fo...

Embodiment 2

[0046] see also Figure 6A to Figure 6D , which is a schematic cross-sectional view of Embodiment 2 of the semiconductor package structure and its manufacturing method of the present invention.

[0047] like Figure 6A As shown, a lead frame 51 is provided with a plurality of pins 511 , and a concave structure 513 is formed on the inner bottom surface of each of the pins 511 , and the semiconductor chip 50 is placed on the pins 511 . The semiconductor chip 50 has an active surface 50a and an opposite passive surface 50b, and the semiconductor chip 50 is connected to the lead frame 51 with its passive surface 50b, and the active surface 50a of the semiconductor chip is provided with a bonding pad 500 .

[0048] like Figure 6B As shown, a substrate 54 is placed on the active surface 50a of the semiconductor chip, and the substrate 54 is provided with an opening 541 corresponding to the welding pad 500 arranged on the active surface 50a of the semiconductor chip, so that the w...

Embodiment 3

[0053] see also Figure 7 , which is a schematic cross-sectional view of Embodiment 3 of the semiconductor package structure of the present invention.

[0054] Embodiment 3 of the present invention is substantially the same as Embodiment 1 above, the main difference is that the size of the substrate 54 is larger than the size of the semiconductor chip 50, for the semiconductor chip 50 to be placed on the pin 511 of the lead frame 50, and to be connected to the semiconductor chip 50. The substrate 54 on the chip 50 is electrically connected to the pin 511 through the bonding wire 52 ′.

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PUM

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Abstract

The invention discloses a semiconductor packaging structure and a manufacturing method thereof. The semiconductor packaging structure includes: a semiconductor chip having an active surface and a relatively non-active surface, a substrate combined on the active surface of the semiconductor chip, and a soldering wire electrically connected to the semiconductor chip. The pad and the bonding wire of the substrate, the lead frame with multiple pins and the encapsulant covering the semiconductor chip, the substrate and the lead frame. Compared with the above-mentioned prior art, the semiconductor packaging structure of the present invention and its manufacturing method can indeed be used to package various semiconductor chips with different pad arrangements, forming a packaging structure with no protruding pins and having the characteristics of lightness, thinness and shortness. Passive components are connected to increase the electrical function.

Description

technical field [0001] The invention relates to a semiconductor packaging structure and its manufacturing method, in particular to a semiconductor packaging structure with an integrated lead frame and its manufacturing method. Background technique [0002] The traditional thin small outline package (Thin Small Outline Package, TSOP) is mainly to connect the semiconductor chip on a lead frame with multiple pins on both sides, and then use the encapsulant to cover the semiconductor chip, so as to use two The exposed part of the side pin is electrically connected with the outside world. [0003] like figure 1 As shown, it is a schematic cross-sectional view of a traditional TSOP, including a lead frame 11, which has a chip holder 111 and a plurality of pins 112 arranged on both sides of the chip holder 111; on the semiconductor chip 10, and the semiconductor chip 10 is electrically connected to the pin 112 by the bonding wire 12; and an encapsulant 13 for covering the chip 10...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/488H01L23/31H01L21/60H01L21/56
CPCH01L24/97H01L2224/32245H01L2224/48091H01L2224/48247H01L2224/48257H01L2224/4826H01L2224/73215H01L2224/97H01L2924/01005H01L2924/01006H01L2924/01015H01L2924/01033H01L2924/01082H01L2924/181H01L2924/19107H01L2924/00014H01L2224/85H01L2924/00012
Inventor 黄建屏张锦煌
Owner SILICONWARE PRECISION IND CO LTD