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Lateral LUBISTOR structure and method

A technology of vertical components and electrodes, applied in the field of electrostatic discharge protection devices, can solve problems such as FINFET processing incompatibility

Inactive Publication Date: 2009-02-04
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This structure is incompatible with FINFET structure and FINFET processing

Method used

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  • Lateral LUBISTOR structure and method
  • Lateral LUBISTOR structure and method
  • Lateral LUBISTOR structure and method

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Experimental program
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Effect test

Embodiment Construction

[0014] ESD LUBISTOR structures based on FINFET technology use vertical fins (50) (thin vertical members containing the source, drain and body of the device), with and without gates (60) in alternative embodiments. The gate (60) can be connected to a protected external electrode (51) to make a self-excited device, or it can be connected to a reference voltage (92). The device can be used in digital or analog circuits.

[0015] The benefits that may arise from one or more preferred embodiments of the present invention are as follows:

[0016] Provides an ESD resistant structure, which is compatible with FINFET semiconductor process and structure;

[0017] Use ESD-resistant FINFET structure and support structure;

[0018] Fins are provided with diode terminals separated by the body, controlled by gate or not, with features such as p + / p - / n + ,p + / n - / n + or p + / p - / n - / n + doping structure;

[0019] provide laterally gated diodes formed on a layer of insulato...

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Abstract

An ESD LUBISTOR structure based on FINFET technology employs a vertical fin (50) (a thin vertical member containing the source, drain and body of the device) in alternatives with and without a gate (60). The gate (60) may be connected to the external electrode (51) being protected to make a self-activating device and may be connected to a reference voltage (92). The device may be used in digital or analog circuits.

Description

technical field [0001] The present invention relates generally to the field of integrated circuit fabrication, and in particular to the fabrication of devices for electrostatic discharge protection (ESD) in integrated circuit technology using FINFETs (Fin Field Effect Transistors). Background technique [0002] FINFET is a promising integrated circuit technology that uses thin (10nm-100nm) vertical members as the source, drain and body of a field effect transistor (FET) and has a gate that is connected to two vertical sides adjacent to the top of the channel. With such a thin body, there is very strong gate coupling, making it easy to achieve fully depleted operation. These structures will require protection from overvoltages caused by EOS electrical overstress, such as electrostatic discharge (ESD) and other voltage and current related overload phenomena during semiconductor manufacturing, shipping and testing. EOS phenomena include over-current overloads, latch-up overlo...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/62H01L27/01H01L21/336H01L27/02H01L27/12H01L29/739H01L29/78H01L29/786
CPCH01L29/7391H01L29/785H01L29/78684H01L27/0255H01L2029/7857H01L29/7841H01L27/1203
Inventor 杰克·曼德尔曼史蒂文·H·沃尔德曼
Owner GLOBALFOUNDRIES INC