Structure and method for semiconductor integrated circuit tunnel oxidation window region design
An integrated circuit and area technology, applied in semiconductor devices, semiconductor/solid-state device manufacturing, circuits, etc., can solve the problems that the channel oxide window cannot be reduced and the device density increases, so as to improve the channel oxide window and increase the device density , Simplify the effect of traditional technology
Active Publication Date: 2009-02-11
SEMICON MFG INT (SHANGHAI) CORP +1
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That is to say, the channel oxide window often cannot be reduced below 0.4 microns, which limits the further increase of device density. These and other limitations will be detailed later.
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[0014] The present invention provides a kind of manufacturing method of the integrated circuit in the semiconductor device production, more specifically, the present invention provides a kind of application FLOTOX technology, the method and the device that make a window structure in the channel dielectric layer of EEPROM device, It should be recognized, however, that the invention has broader utility as well.
[0015] Figure 1 to Figure 3 A method for forming a channel oxidation window in a conventional EEPROM device is illustrated; as shown in the figure, the conventional method first provides a substrate 100 including a substrate surface region 101, which is located between two isolation regions 103, Isolation regions are usually implemented using localized oxidation, commonly referred to as LOCOS. The method then overlies the surface region with a dielectric layer 201, which is typically patterned to form a channel window 205, which is a surface region that is thinner than...
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A structure of design for semiconductor IC channel oxidation window area and method thereof, said structure contains a substrate with surface area in a first unit area, a grid dielectric layer with first thickness covered on substrate, a selective grid covered on first area of said grid dielectric layer, a float grid covered on second area of said grid dielectric layer and coupled with said selective grid, an insulation layer covered on float grid, a control grid covered on the insulation layer of float grid and coupled with said float grid, a pass way window located in strap shaped structure of grid dielectric layer area which is smaller than said first and second thickness. Said invention simplifies traditional technology, raises device productivity and density and is compatible with current preparation process.
Description
technical field [0001] The present invention relates to an integrated circuit in the production of semiconductor devices and a method of manufacturing the same. Specifically, the present invention provides a method and apparatus for fabricating a window structure in the channel dielectric layer of an EEPROM device using FLOTOX technology, but it should be recognized that the present invention also has broader applications. Background technique [0002] A variety of memories have been applied or proposed in the industry. Erasable read-only memory (EPROM) is an example. EPROM is both readable and erasable, and can be programmed. In particular, an EPROM employs a floating gate FET that has a binary state, ie the presence or absence of charge on the floating gate represents the binary state. Even when a typical high voltage signal is applied to the gate of the EPROM, the charge on the floating gate is sufficient to prevent conduction. [0003] EPROM has many specifications and...
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IPC IPC(8): H01L27/115H01L21/8247H01L29/788H10B69/00
CPCH01L27/11524H01L27/11521H01L29/7883H01L27/115H10B69/00H10B41/30H10B41/35
Inventor 吴佳特蔡建祥
Owner SEMICON MFG INT (SHANGHAI) CORP