Semiconductor storage device and semiconductor storage device bit line selection method

Abstract

A image display apparatus such as a plasma display panel or the like wherein false contours of moving images can be suppressed with sufficient gray scale maintained. The image display apparatus includes a disturbance constant adding circuit (19) that generates a plurality of disturbance constants for the gray scale corresponding to an image signal and that selects and adds one of those disturbance constants to the image signal. Thus, disturbance is applied to and superimposed on each image signal, thereby scattering locations where false contours of moving images occur so as to make those false contours visually unnoticeable.

Description

technical field [0001] The present invention relates to a bit line selection technology of a semiconductor storage device, in particular to a bit line selection technology when a plurality of bit lines are sequentially and continuously selected. Background technique [0002] Conventionally, in a semiconductor memory device, after dividing a memory cell array into a plurality of sub-arrays, data is read out by sequentially selecting one bit line from a plurality of bit lines provided in each sub-array. Continuous readout operation such as character group readout and storage. [0003] Here, FIG. 11 shows a circuit configuration in which a nonvolatile semiconductor storage device such as a flash memory is taken as an example as shown in Patent Document 1. As shown in FIG. The memory cell array is divided into sub-array AA (identified by low-level column address A (k+4)) and sub-array AB (identified by high-level The sub-array identified by the column address A(k+4) of the lev...

AI Technical Summary

Problems solved by technology

However, for the wiring of shield lines, it is necessary to secure a new wiring area parallel to the bit lines in the memory cell array, which is not desirable in terms of chip integration.

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