Solid-state image pickup device and method for driving the same
A solid-state image pickup and equipment technology, applied in image communication, color TV parts, TV system parts and other directions, can solve the problems of reduced sensitivity, reduced sensitivity of imaging results, etc., to prevent the reduction of sensitivity and increase the frame rate. effect of speed
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no. 1 example
[0042] figure 1 is a block diagram showing the structure of a solid-state image pickup device such as a CMOS image sensor 10 including a column-parallel ADC according to a first embodiment of the present invention. Such as figure 1 As shown, the CMOS image sensor 10 according to this embodiment includes a pixel array unit 12, wherein each unit pixel 11 including a photoelectric converter is two-dimensionally arranged in a matrix mode; a row scanning circuit 13, a column processing unit 14; a reference voltage a supply circuit 15; a column scanning circuit 16; a horizontal output line 17; and a timing control circuit 18.
[0043] In this system configuration, the timing control circuit 18 generates clock signals and controls used as working references for the row scanning circuit 13, the column processing unit 14, the reference voltage supply unit 15, the column scanning circuit 16, etc. based on the master clock MCK. signals, and provide these signals to the row scanning c...
no. 2 example
[0091] Figure 6 Shown is a block diagram of the structure of a CMOS image sensor 50 including a column-parallel ADC according to a second embodiment of the present invention. The timing chart shown in FIG. 7 illustrates the operation of the CMOS image sensor 50 according to this embodiment.
[0092] The structure of the CMOS image sensor 50 including the column-parallel ADC according to this embodiment is basically the same as that according to figure 1 The structure of the CMOS image sensor 10 including the column-parallel ADC of the first embodiment shown is the same. The difference between them is that the row scanning circuit 13A includes an address decoder capable of selecting any one of the row control lines 21-i (21-1 to 21-n). The row scanning circuit 13A comprising the address decoder can select the row control line 21-1 in the order of, for example, the first row, the third row, the second row, the fourth row, . . . as shown in FIG. 7 to 21-n.
[0093] In such ...
no. 3 example
[0098] Figure 8 Shown is a block diagram of the structure of a CMOS image sensor 60 including a column-parallel ADC according to a third embodiment of the present invention. exist Figure 8 in, with as figure 1 Like parts are shown with like reference numerals.
[0099] The structure of the CMOS image sensor 60 including the column-parallel ADC according to this embodiment is basically the same as that according to figure 1 The CMOS image sensor 10 including the column-parallel ADC of the first embodiment shown is the same. They differ in the following respects.
[0100] The output of each ADC 23-1, 23-3, . . . connected to odd-numbered column signal lines 22-1, 22-3, . . . , is output through an N-bit-width horizontal output line 17-1. Similarly, the output of each ADC23-2, 23-4, ..., connected to the even-numbered column signal lines 22-2, 22-4, ..., passes through the horizontal output line 17-2 of N-bit width output. The digital signal of the odd-numbered row out...
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