Semiconductor packaging device

Abstract

This invention relates to semi-conductor sealing device, which comprises one baseboard, one first chip, one non-conductive glue, one second chip and multiple supportive sphere, wherein, the first chip has relative upper and down surfaces fixed on the baseboard; the non-conductive glue is set on the top surface of the first chip; the second chip has relative top and down surfaces, wherein, the said down surface is fixed on the top surface of the first chip through non-conductive glue with adherent area between the non-conductive glue and the second chip is larger than the down surface area; the multiple supportive sphere located on the non-conductive glue to support the second chip.

Description

technical field [0001] The invention relates to a packaging device, in particular to a semiconductor packaging device. Support balls are arranged in the non-conductive adhesive between two stacked chips to define the space required for bonding wires, and to make the non-conductive adhesive adhere to the upper chip. The area is greater than 90% of the lower surface area of ​​the upper chip, so as to reduce the structural stress concentration after the sealing process, thereby avoiding chip crack (die crack) and increasing the yield rate of the package. Background technique [0002] With increasing demands for miniaturization and high operating speed, Multi-Chip Module Package (MCM Package) is becoming more and more attractive in many electronic devices. The multi-chip packaging device can combine two or more chips into a single packaging device, so that the volume of the whole system is minimized and has a higher storage capacity. For example, combining two DRAM memory chips...

AI Technical Summary

Problems solved by technology

However, the fiberglass-reinforced resin layer is made of soft material, so the fiberglass-reinforced resin layer cannot completely define the space required for the wire bonding, such as a height above about 5 mils.

[0007] In addition, the US patent document US2003 / 0160311A1 discloses a semiconductor package comprising an upper integrated circuit die and a bottom integrated circuit die, the lower surface of the upper integrated circuit die is connected to the upper surface of the bottom integrated circuit die by an adhesive material. Connected, the bonding material includes a plurality of particles mixed therein to maintain a predetermined spacing between the upper integrated circuit die and the bottom integrated circuit die to avoid damage to the wires, the particles can be of any shape, but the arrangement is not neat and close

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