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Chip package structure

A chip packaging structure and chip technology, applied in the direction of electrical components, electrical solid devices, circuits, etc., can solve the problems of long distance, short circuit, false contact, etc., and achieve the effect of avoiding short circuit

Active Publication Date: 2009-07-01
UNITED MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] It should be noted that since the distance between the second wire 134 and the second pad 132 and the second contact 114 is very long, and crosses over the first wire 124, once the second wire 134 and the first wire When the line distance between 124 is shortened or the molding flow (molding flow) hits the second wire 134 to cause sweeping (sweeping), the first and second wires 124 and 134 of different levels are prone to false contact and short circuit

Method used

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  • Chip package structure
  • Chip package structure
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Embodiment Construction

[0039] Please refer to figure 2 , which is a schematic top view of the chip package structure according to the first embodiment of the present invention. The chip package structure 200 is a wire-bonded stacked chip package structure, which includes a substrate 210 , a first chip 220 and a second chip 230 on the first chip 220 . It should be noted that although the second chip 230 is arranged on the first chip 220, it is not located on the symmetrical center of the first chip 220, that is, the second chip 230 is not in the central area of ​​the first chip 220, but in the first chip 220. A corner area of ​​the chip 220. In this embodiment, the second chip 230 is located in the upper left corner area of ​​the first chip 220, but in another embodiment (not shown), the second chip 230 can also be on one side of the first chip 220 Border area, its position can be adjusted appropriately.

[0040] In this embodiment, the first chip 220 sets the position and quantity of the first b...

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Abstract

The chip package structure comprises: a base, including multiple first / second joint points arranged on the first / second side area of base; a first chip arranged on the base, which includes multiple first welding pads on the first wire bonding area near the first joint points to cross over the first joint points and pad by first wire; and a second chip set on but not the symmetrical center of the first chip, which includes multiple second welding pads on the second wire bonding area near the second joint points to cross over the second joint points and pad by second wire.

Description

technical field [0001] The present invention relates to a chip packaging structure, in particular to a chip stacked (stacked) packaging structure. Background technique [0002] In the semiconductor industry, the development of system-on-chip (SOC) packaging is affected by process yield and high cost, and cannot be mass-produced. It is replaced by a chip stack package structure with a higher yield rate, which can meet the specifications of a chip size package (CSP) to meet the needs of general small electronic devices. [0003] figure 1 A schematic diagram of wire bonding of a conventional chip packaging structure is shown. The chip packaging structure 100 includes a substrate 110 , a first chip 120 and a second chip 130 on the first chip 120 . The first bonding pad 122 on the first chip 120 of the lower layer is connected to the first contact 112 of the substrate 110 with a plurality of first wires 124, which belongs to the first level of wire bonding, while the second pa...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L25/00H01L25/065H01L23/488
CPCH01L2224/48091H01L2224/49431H01L24/06H01L2224/05553H01L2924/181H01L2924/00014H01L2924/00012
Inventor 吴炳昌
Owner UNITED MICROELECTRONICS CORP