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Adaptive voltage scaling clock generator for use in a large scale digital processing component and method of operating the same

A technology of digital circuits and clock generators, applied in the directions of data processing power supply, electrical digital data processing, digital data processing components, etc., can solve problems such as consumption

Inactive Publication Date: 2009-07-08
NAT SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

But at a VDD level of +3.3 volts, the CPU or DSP can consume far more power than necessary to operate at 100 MHz

Method used

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  • Adaptive voltage scaling clock generator for use in a large scale digital processing component and method of operating the same
  • Adaptive voltage scaling clock generator for use in a large scale digital processing component and method of operating the same
  • Adaptive voltage scaling clock generator for use in a large scale digital processing component and method of operating the same

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Embodiment Construction

[0030] The present invention is described in detail below. The appendix discussed below Figure 1 to Figure 9 , and the various examples used to illustrate the principles of the present invention in this patent document are for illustrative purposes only and should not be construed as limiting the scope of the invention in any way. Those skilled in the art will understand that the principles of the invention may be implemented in any suitably arranged digital processing system.

[0031] figure 1 A block diagram of a digital processing system 100 according to one embodiment of the present invention is shown. The digital processing system 100 includes a crystal oscillator 105, a phase-locked loop (PLL) frequency synthesizer 110, an adaptive voltage scaling (AVS) clock generator 115, a digital signal processor / central processing unit (DSP) / CPU) system digital processing unit 120, adaptive voltage scaling (AVS) relaxation time detector 125 and adaptive voltage scaling (AVS) po...

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PUM

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Abstract

The present invention discloses a clock control circuit (705, 710, 715) for selectively applying a clock signal to a digital processing unit (100), wherein the clock signal can be converted into multiple operating frequencies, the clock control circuit (705, 710, 715) are operative to (i) accept an instruction to change the first operating frequency to a second operating frequency; (ii) in response to the instruction, disable the applied clock signal; (iii) generating a test clock signal with a second operating frequency; (iv) adding the test clock signal to a power conditioning circuit (125), and (v) sensing a status signal from the power conditioning circuit (125) . The status signal indicates that a power supply level of the digital processing unit (100) has been adjusted to an optimum value for the second operating frequency.

Description

technical field [0001] The general direction of the invention is towards low power integrated circuits. More specifically, it is directed towards a system and method of operation for regulating the power supply level of a digital processing unit. Background technique [0002] In recent years, integrated circuits (IC) have made great progress in terms of speed, power and complexity, such as application-specific integrated circuit (ASIC) chips, central processing unit (CPU) chips, digital signal processor (DSP) chips, etc. , these advances, among other things, have enabled the development of a system-on-a-chip (SOC). A SOC system-on-a-chip device can integrate all (or nearly all) components of a complex electronic system into a single chip, such as a wireless receiver (ie, cellular phone, television receiver, etc.). [0003] An important criterion for evaluating electronic devices is power consumption, and minimizing power consumption has long been an important design consid...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F1/32G06F1/08
CPCG06F1/08Y02B60/1285G06F1/3203G06F1/3296G06F1/324Y02B60/1217Y02D10/00
Inventor 布鲁诺·克兰兹恩德雷根·麦克斯莫维克
Owner NAT SEMICON CORP
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