Method of simultaneous formation of charge storage and bitline to wordline isolation layer

Abstract

The present invention relates to a method of forming a non-volatile semiconductor memory device, the method comprising forming a charge trapping dielectric (14) on a base substrate (12) in successive or discontinuous steps, the substrate A material substrate (12) has a central region (16) and a peripheral region (18); at least a portion of the charge trapping dielectric (14) in the peripheral region (18) is removed; in the peripheral region (18) Forming a gate dielectric (22) in the central region (16); forming a buried bit line (26) in the central region (16); and forming a gate (28) in the central region (16) and the surrounding region (18) .

Description

technical field [0001] The present invention relates to the field of fabrication of non-volatile memory components, and more particularly to an improved method of fabricating non-volatile memory components of the silicon oxynitride silicon (SONOS) type. Background technique [0002] The existing electrically erasable programmable read-only memory (EEPROM, Electrically Erasable Programmable Read-Only Memory) floating gate (Floating gate) flash memory type uses a vertically stacked tunnel oxide layer (Tunnel Oxide). A first polysilicon layer (first polysilicon layer) on the tunnel oxide layer, a silicon dioxide / silicon nitride / silicon dioxide (Oxide / Nitride / Oxide, ONO) inner layer on the first polysilicon layer Dielectric layer, and a memory cell characterized by a second polysilicon layer on the ONO interlayer dielectric layer. For example, Guterman et al. in 1979, Institute of Electrical and Electronics Engineers (IEEE) Electronic Components Transactions, Vol. 26, No. 4, p....

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Problems solved by technology

Thus, diffusion due to thermal cycling will result in an unintended amount of leakage between bitlines

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