Method for manufacturing fin-shaped field effect transistor by epitaxial process

Abstract

The present invention provides a method of processing fin field effect transistor by using epitaxial-selected process, and belongs to field of semiconductor integrated circuit processing technology. The method uses SOI wafer as substrate. A thin media layer is firstly growth on surface of the substrate; secondly, semiconductor strip is formed by lithographing or etching the thin media layer and SOI semiconductor film layer; thirdly, central part of the semiconductor strip is heavily doped; fourthly, the semiconductor strip is taken as substrate to epitaxial grow un-doped semiconductor film which is formed on two sides of the semiconductor strip; thin media layer on top of the semiconductor strip and heavily doped part of the central semiconductor strip are etched, and semiconductor film of two sides of the semiconductor strip and the un-doped area of two sides of the semiconductor strip are left; finally, the semiconductor film is taken as super thin Fin to grow gate media layer and gate electrode material and process super-thin-Fin field effect transistor. The Fin thickness in the present invention is decided by epitaxial processing, therefore the Fin thickness, uniformity of the Fin shape can be both largely increased and improved.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits and its manufacture, and in particular relates to a method for preparing a Fin Field Effect Transistor (FinFET). Background technique [0002] Since the invention of the integrated circuit, its performance has steadily improved. The increase in performance is mainly achieved through the continuous shrinking of the size of integrated circuit devices. Currently, the feature size of integrated circuit devices (MOSFETs) has shrunk down to the nanometer scale. At this scale, various basic and practical limitations begin to appear, making the development of integrated circuit technology based on silicon planar CMOS technology encounter unprecedented challenges. It is generally believed that after hard work, CMOS technology is still possible to advance to the 20nm or even 10nm technology node, but after the 45nm node, the traditional planar CMOS technology will be difficult to...

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Problems solved by technology

Due to the poor uniformity and repeatability of the geometric dimensions of the formed graphics, this technology cannot be used in the production of circuits.

Although spacer image transfer is a simple nano-scale processing technology that can be used to make a single device, this technology will produce many parasitic patterns, so it cannot be used in the production of circuits.

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