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Execution of hardware description language (HDL) programs

A hardware description language, program technology, applied in program control design, software engineering design, CAD circuit design, etc., can solve the problems of low speed, high power consumption, high cost and so on

Inactive Publication Date: 2009-09-23
COHERENT LOGIX
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This is because lower speed, higher power consumption, and higher cost are less important in such systems in order to obtain faster operation cycles

Method used

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  • Execution of hardware description language (HDL) programs
  • Execution of hardware description language (HDL) programs
  • Execution of hardware description language (HDL) programs

Examples

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Embodiment Construction

[0037] Overview of HDL Execution System

[0038] In one embodiment, an HDL description of an electronic system is compiled into object code (e.g., one or more programs, each program comprising a plurality of instructions in an instruction set architecture executed by a processor), the instructions being downloaded to a or multiple instruction memories and executed by the processor system. The processor system may be implemented in a single chip or in multiple chips of the target electronic system. The HDL can be any high-level language (eg, Verilog, VHDL, C language derivatives, etc.). The instruction set architecture executed by the processor system may support arithmetic / logic instructions (or bit manipulation instructions) and control flow instructions (eg, branch instructions and special conditional branch instructions).

[0039] Processor System Architecture

[0040] In one embodiment, a processor system includes an interconnected array of processors. Each process...

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Abstract

The present invention relates to the execution of hardware description language (HDL) programs. In one embodiment, hardware implementation of an electronic system may be achieved by compiling an HDL description into an executable form and executing processor instructions. In some implementations, by applying data flow separation techniques, the operations of the system can be effectively mapped to the instruction set of a complex processor for efficient logic evaluation. In some embodiments, arrays of interconnected processors may be employed to take advantage of the parallelism inherent in HDL descriptions.

Description

technical field [0001] The present invention relates to hardware implementation of an electronic system described in a hardware description language (HDL), and more particularly to a compiling method and a multiprocessor architecture for implementing hardware of an electronic system. Background technique [0002] The functionality of modern electronic systems implemented as integrated circuits is often expressed in a hardware description language (HDL). The purpose of HDL is to provide designers with a productive design medium that expresses the functionality of a system in an unambiguous form, which can then be simulated to verify the correctness of the design before turning it into hardware. Various techniques now exist for converting such HDL descriptions into actual hardware implementations. The traditional way to achieve hardware implementation described by HDL is: [0003] 1. Custom Application Specific Integrated Circuit (ASIC) [0004] The main steps of a custom A...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F17/50G06F9/45
CPCG06F17/5045G06F17/5022G06F8/457G06F30/30G06F30/33G06F30/3308
Inventor 汤米·K·恩格
Owner COHERENT LOGIX