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Method for forming passivation layer of CMOS device

A passivation layer and device technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems affecting process progress

Inactive Publication Date: 2009-11-18
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, actual production finds that, as Figure 5 As shown, after undergoing the step of removing part of the second stress passivation layer and the dielectric layer to form the CMOS device passivation layer, at the junction of the first stress passivation layer and the second stress passivation layer A bump 60 is formed, which affects the progress of the subsequent process

Method used

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  • Method for forming passivation layer of CMOS device
  • Method for forming passivation layer of CMOS device
  • Method for forming passivation layer of CMOS device

Examples

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no. 1 example

[0063] Such as Figure 6 As shown, as the first embodiment of the present invention, the specific steps of applying the method provided by the present invention to form a CMOS device passivation layer include:

[0064] Step 601: Provide a semiconductor base, the semiconductor base includes at least one CMOS device, and the CMOS device includes at least one NMOS transistor and at least one PMOS transistor.

[0065] Such as Figure 7 As shown, for the sake of simplicity, only the gate structure 102 of the NMOS transistor 120 and the PMOS transistor 140 is shown in the figure, and the gate structure 102 includes the gate and the sidewall (offset spacer) surrounding the gate, but not shown Its source and drain, as well as the gate oxide and STI isolation trenches in the substrate. A CMOS device is located on a semiconductor substrate 100, the CMOS device includes at least one NMOS transistor 120 and at least one PMOS transistor 140, the substrate includes but is not limited to s...

no. 2 example

[0089] As a second embodiment of the present invention, the specific steps of applying the method provided by the present invention to form a CMOS device passivation layer include:

[0090] First, a semiconductor body is provided, the semiconductor body includes at least one CMOS device, and the CMOS device includes at least one NMOS transistor and at least one PMOS transistor.

[0091] Subsequently, a compressive stress film covering the NMOS transistor and the PMOS transistor is formed, and a compressive stress body is formed on the PMOS transistor.

[0092] Afterwards, the compressive stress film layer covering the NMOS transistor is removed.

[0093] Then, a tensile stress film covering the compressive stress film and the NMOS transistor is formed, and a tensile stress body is formed on the NMOS transistor.

[0094] Furthermore, a sacrificial layer is formed, the sacrificial layer covers the tensile stress body, and fills the space area between the tensile stress body and...

no. 3 example

[0100] Such as Figure 16 As shown, as the third embodiment of the present invention, the step of applying the method provided by the present invention to form a CMOS device passivation layer includes:

[0101] Step 1601: if Figure 17 As shown, a semiconductor body comprising at least one CMOS device comprising at least one NMOS transistor 122 and at least one PMOS transistor 142 is provided.

[0102] For the sake of simplicity, only the gate structure 112 of the NMOS transistor 122 and the PMOS transistor 142 is shown in the figure, and the gate structure 112 includes the gate and the sidewall (offset spacer) surrounding the gate, and the source thereof is not shown. and drain, and STI isolation trenches in the gate oxide and substrate. A CMOS device is located on a semiconductor substrate 110, the CMOS device includes at least one NMOS transistor 122 and at least one PMOS transistor 142, the semiconductor substrate 110 includes but is not limited to silicon materials incl...

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Abstract

A method for forming a passivation layer of a CMOS device, comprising: providing a semiconductor base, the semiconductor base includes at least one first transistor and at least one second transistor; forming a first stress film layer, and forming a first stress body; The first stress film layer of the second transistor; forming the second stress film layer and forming the second stress body; forming the second stress body covering the second stress body and filling the second stress body and the first stress film layer that has covered the second stress film layer A spacer area between stressors, and the sacrificial layer whose surface is flush with the upper surface of the first stressor after covering the second stressor film layer; form a patterned resist layer; use the resist layer as a mask, remove part of the sacrificial layer and the second stress film layer; remove the resist layer; use the first stress film layer as an etching stop layer, remove the sacrifice layer and part of the second stress film layer. The smoothness of the junction between passivation layers with different stress types can be made to meet the process requirements.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to a method for forming a passivation layer of a CMOS device. Background technique [0002] At present, it is well known in the industry that there is the following piezoresistive effect: the stress generated in the semiconductor film layer can cause the lattice interval in the film layer to change, which in turn leads to the change of the energy band structure, and then the carrier mobility changes . Whether the carrier mobility becomes larger or smaller depends on the plane direction of the substrate, the direction of carrier movement, and the type of stress including tensile stress and compressive stress. For example, in a silicon substrate with the (100) plane as the main surface, when the moving direction of the carriers is the (011) direction, if the carriers are electrons, if the electrons in the channel region move When tensile stress is generated ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8238
Inventor 张海洋韩秋华韩宝东张世谋
Owner SEMICON MFG INT (SHANGHAI) CORP