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Method for forming dual damascene pattern

A pattern and double technology, applied in the field of forming double mosaic patterns, can solve the problems of high manufacturing cost, complicated insulating film/amorphous carbon layer process, etc.

Inactive Publication Date: 2009-12-30
SK HYNIX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] However, the process of using an insulating film / amorphous carbon layer is complicated
In addition, because of the chemical vapor deposition (CVD) process involved, the manufacturing cost is high

Method used

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  • Method for forming dual damascene pattern
  • Method for forming dual damascene pattern
  • Method for forming dual damascene pattern

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0078] Example 1. Coating experiment of multifunctional hardmask

[0079] Ti / TiN / TiN tungsten and hard mask nitride film Deposited on a semiconductor substrate and etched to form bit line patterns. Multifunctional hardmask film (NCH 087, Nissan Industrial Chemical) was used as The thickness is spin-coated. The cross-sections of the obtained structures were measured using SEM at tilt angles of 60° and 90°.

[0080] At a 90° tilt angle (see Figure 5a ) and 60° tilt angle (see Figure 5b ), forming a multifunctional hard mask film without any voids.

Embodiment 2

[0081] Embodiment 2. Measurement of the reflectivity of the substrate after coating the multifunctional hard mask film

[0082] An HDP oxide film and a multifunctional hard mask film (NCH 087, Nissan Industrial Chemical) were deposited on the underlayer to have thicknesses different from each other. The multifunctional hard mask film is formed by means of a spin-coating method. The substrate reflectance (Y-axis) was measured against the absorbance of the multifunctional hardmask and the coating thickness (X-axis). Figures 6a to 6d Display the result.

[0083] When the coating thickness of the multifunctional hardmask film ranges from about 300 to (k ranges from about 0.3 to 0.6) or from about 800 to (k in the range of about 0.2 to 0.5), the substrate reflectance is less than 1.0%. When the coating thickness of the hard mask film formed over the low dielectric film ranges from about 340 to , k ranges from about 0.4 to 0.5 (see Figures 6a to 6c ).

[0084] Figure 6...

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Abstract

The invention discloses a method for forming a double-embedding pattern, comprising the steps as follow: a multifunctional hard mask compound containing silicon resin as the main agent is prepared; a settlement structure comprising a self-alignment contact insulation film, a first dielectric film, an etching barrier film and a second dielectric film is formed at the upper part of a hard connection layer; the settlement structure is etched till the hard connection layer is exposed so as to form a conductive hole; the multifunctional hard mask compound is formed at the upper part of the second dielectric film and inside the conductive hole so as to form a multifunctional hard mask; and the multifunctional hard mask film is removed.

Description

technical field [0001] Generally, the present invention relates to semiconductor processing. More specifically, the present invention relates to a method of forming a dual damascene pattern. Background technique [0002] As the semiconductor industry develops ultra-large-scale integration (ULSI) devices, devices shrink to sub-half-micron dimensions, which increases circuit density, causing resistance-capacitance (RC) delays and copper reactive ion etching (RIE). During the process of forming bit line patterns for devices with reduced dimensions, the patterns may bridge or collapse. [0003] In order to avoid bridging and / or collapse of patterns and improve the layout of devices, dual damascene processes have been developed. The dual damascene process can be used when it is not possible to pattern the metallic material with conventional etch techniques due to device size reduction, or when filling low-k dielectric materials to form conventional metal lines in a deep contact...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L21/311
CPCG03F7/091H01L21/3122H01L21/31144H01L21/0276H01L21/76808H01L21/28
Inventor 李基领许仲君
Owner SK HYNIX INC