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Method for monitoring silicon monocrystal extension layer fault situation using micro-image region iterated logarithm measuring apparatus

A technology for stacking measurement and monitoring silicon, which is applied in the field of stacking fault monitoring, and can solve problems such as loss, abnormal jumps in measurement data after imaging stacking, and measurement results cannot be quantified.

Inactive Publication Date: 2010-05-12
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] At present, the frequency of detection of stacking faults (Slip) on the single crystal epitaxial layer is about once a week, and Fourier transform infrared spectroscopy is required for detection. What is more inconvenient is that the measurement results cannot be quantified and can only be judged manually through macro pictures
[0006] To sum up, although the current monitoring results of silicon single crystal epitaxial stacking faults (Slip) can provide us with a macroscopic picture, it also requires the operator to make human judgments, and quantitative information cannot be fed back. The overlay measurement (Overlay) data of the rear imaging layer jumps abnormally, causing irreparable losses

Method used

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  • Method for monitoring silicon monocrystal extension layer fault situation using micro-image region iterated logarithm measuring apparatus
  • Method for monitoring silicon monocrystal extension layer fault situation using micro-image region iterated logarithm measuring apparatus
  • Method for monitoring silicon monocrystal extension layer fault situation using micro-image region iterated logarithm measuring apparatus

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Experimental program
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Embodiment 1

[0026] Test Wafer Preparation

[0027] The test wafer must define the zero mark before use, first define the 0-layer mark in the lithography area (Photo), and etch the 0-layer mark on the wafer (wafer) surface in the etching area (Etch). When monitoring is required Then deposit silicon single crystal epitaxy on the pre-prepared test wafer, and then define the first layer of marks on the test wafer in the lithography area.

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Abstract

This invention discloses one method to monitor silicon single crystal extensive layer overlapping in the microscope area, which comprises the following steps: processing large volume of overlap labelon crystal slice surface and comparison slice; by use of overlap device to test the slice exposure definition in microscope area for overlap label to find out overlap cross.

Description

technical field [0001] The invention relates to the field of monitoring the stacking fault (Slip), in particular to a method for monitoring the status of the silicon single crystal epitaxial stacking fault (Slip) by using a lithography area overlay measuring instrument. Background technique [0002] Stacking fault (Slip) refers to a certain crystal crack displacement, which is the growth that deviates from the original crystal lattice direction at certain positions during the growth of single crystal epitaxy (Epitaxial silicon). When the temperature of the wafer rises rapidly, the wafer will bear greater temperature stress. Once the temperature of a certain area on the crystal is significantly hotter or colder than the rest of the area, the crystal can release excess temperature pressure through the fault (Slip). [0003] In a single crystal epitaxial (Epitaxial silicon) sample without stacking faults, the crystal lattice is in a regular arrangement of crystals ( figure 1 ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01N21/958
Inventor 付嵛胡平王燕军于经元
Owner SEMICON MFG INT (SHANGHAI) CORP