Bus watch circuit

Abstract

The present invention discloses a bus line monitoring circuit which comprises the following components: a debug target module, a control circuit, a data sustaining circuit and an inconsistency detecting circuit. The debug object module outputs the input data received from the bus line as the output data and generates the input data effective timing information representing the effective timing of the input data and the output data effective timing information representing the effective timing of the output data. The control circuit generates a sustaining timing signal and a comparing timing signal basing on the input data effective timing information and the output data effective timing information, the sustaining timing signal represents the timing sustaining the input data at the inner side, and the comparing timing signal represents the timing that compares the input data with the output data. The data sustaining circuit sustains the input data in the period sustaining the synchronization of the timing signal. The inconsistency detecting circuit and the comparing timing signal synchronously judge whether the sustaining data of the data sustaining circuit is consistent with the output data.

Description

technical field [0001] The invention relates to a bus monitoring circuit, which is suitable for system debugging and evaluation / improvement of application program performance in information processing equipment and other equipment. Background technique [0002] When the operation of the bus is verified according to a conventional debugging method such as an on-chip debugger (OCD) or an in-circuit emulator (ICE), trace information is output to the outside for debugging. Further, as shown in the Japanese patent document (Japanese Patent Laid-Open Publication No. H05-324495), it is also possible to use such a method that the protocol transition information is stored in the memory device in advance, and whether the protocol is detected by comparing it Illegal use. [0003] When verifying operations of multiple buses according to a conventional debugging method such as an on-chip debugger (OCD) or an in-circuit emulator (ICE), a large number of terminals are required to output t...

AI Technical Summary

Problems solved by technology

However, there is a limit to the number of terminals that can be provided, so it is difficult to monitor two or more internal messages

Further, complicated circuit configurations make it difficult to identify parts where problems such as garbled data due to physical failure or the influence of crosstalk have occurred

According to the method of storing the protocol transition information in the memory device in advance, any illegal behavior in the protocol transition can be detected, however, the part where a problem such as garbled data occurs cannot be detected

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