Embedded system chip and data read-write processing method

An embedded system and chip technology, applied in the field of data processing, can solve the problems of limited memory interface transmission bandwidth, affecting system performance, memory interface congestion, etc., to speed up data access, improve overall performance, and improve the effect of delay conditions.

Active Publication Date: 2008-03-05
HUAWEI TECH CO LTD
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  • Abstract
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Problems solved by technology

[0009] The purpose of the embodiments of the present invention is to provide an embedded system chip, which aims to solve the problem that in the prior art, due to the limited transmission b

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  • Embedded system chip and data read-write processing method
  • Embedded system chip and data read-write processing method
  • Embedded system chip and data read-write processing method

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Embodiment Construction

[0033] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

[0034] In the embodiment of the present invention, a master device interface and a slave device interface are added to the structure of the existing bus crossover module, and the system-level sacrificial cache memory is expanded in a loopback manner to store the latest data written by each master device. The read and write operations of the device are determined by the determination unit and the victim cache. If the determination is satisfied, the read and write operations are completed in the victim cache, which can reduce the amount of data accessed by the memory interface.

[0035] FIG. 4 shows ...

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Abstract

The embedded system chip comprises a sacrifice high speed buffer which uses the fake address never being used in the system and is connected to an interface of master machine and an interface of slave machine in bus crossing module, and is used for saving the data recently written out by the host machine and making decision for the read-write operation on the host machine satisfying the address segment; a decision unit located on the address channel between the bus crossing module and the host machine interface and used for making pre-decision for the address of the host machine read-write operation according to the address segment of the sacrifice high speed buffer, and sends the read-write operation satisfying the address segment of the sacrifice high speed buffer to the sacrifice high speed buffer, and modifying the host machine read-write operation address into the fake address, and sending the fake address to the bus crossing module. The invention can reduce the data traffic accessing the memory interface.

Description

technical field [0001] The invention belongs to the field of data processing, in particular to an embedded system chip and a data reading and writing processing method. Background technique [0002] As the design of embedded system chips (System on Chip, SoC) becomes more and more complex, new requirements including multi-processor multi-service model collaboration, data flow optimization, frequency increase, etc., make SoC from the previous Data Processing Centric evolved to Data Flow Centric. Existing interconnection protocols such as Advanced High-performance Bus (AHB) have many limitations, and the huge load brought by multiple master devices (Masters) competing for the bus reduces the effective rate of data; cannot support embedded The more advanced instruction execution mechanism of the traditional processor, such as the mechanism that the cache (Cache) can continue to hit in the case of failure; the delay caused by the ultra-long logic path on the original bus archit...

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Application Information

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IPC IPC(8): G06F12/08G06F12/0868
Inventor 夏晶
Owner HUAWEI TECH CO LTD
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