Self-aligning stacked grid and its manufacturing method
A manufacturing method, a technology of stacked gates, applied in semiconductor/solid-state device manufacturing, electrical components, transistors, etc.
Inactive Publication Date: 2008-05-07
POWERCHIP SEMICON CORP
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Problems solved by technology
In this way, the existing process will not be conducive to the reduction of the size of the memory cell, especially for the reduction of the STI shallow trench isolation structure is the most unfavorable
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[0073] The examples described in this paragraph are used to explain the present invention, but not to limit the present invention. The invention is not limited to particular materials, processing steps or dimensions. The invention is defined by the appended claims.
[0074] see Figure 3(A) to Figure 3(J) , which discloses a schematic flowchart of a method for manufacturing a self-aligned stacked gate according to a preferred embodiment of the present invention. First, as shown in FIG. 3(A), a substrate 31 is provided, and a first dielectric layer 32 , a first conductive layer 33 and a shielding layer 34 are sequentially formed on the substrate. Wherein the first dielectric layer 32 is a gate oxide layer in this embodiment, which can oxidize the substrate 31 at a high temperature through a thermal oxidation process to form an oxide layer with a desired thickness. The first conductive layer 33 is used as a floating gate unit in this embodiment, and may be an inherent polysil...
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The invention provides a manufacturing method for a self-aligned stack gate used in read-only (or non-volatile memory) memories, which comprises the following steps: a) a substrate is provided; b) a first dielectric layer, a first conductive layer and a shielding layer are successively formed on the substrate; c) the shielding layer, the first conductive layer, the first dielectric layer and the substrate are partly etched to form a shallow trench; d) a second dielectric layer is used to fill the shallow trench to form a shallow trench isolation (STI) unit, and the shielding layer is removed; e) a second conductive layer is fully formed; f) the second conductive layer is partly etched to form a side wall together with the first conductive layer; g) a part of the shallow trench isolation unit is removed to expose a part of the side wall between the second conductive layer and the first conductive layer; h) a third dielectric layer and a third conductive layer are deposited in order, and i) the third conductive layer is partly etched, and thus a self-aligned stack gate with high coupling ratio is acquired.
Description
technical field [0001] The invention relates to a manufacturing method of a non-volatile storage body, in particular to a manufacturing method applied to a self-aligned stack gate in a non-volatile storage body. Background technique [0002] Among all kinds of memory products in the industry today, the programmable non-volatile memory (erasable programmable read-only memory, EPROM) has the ability to write, read and erase data multiple times, and The stored data has the advantage that it will not disappear after power failure, so it has become a storage body component widely used in personal computers and electronic equipment. [0003] A typical programmable non-volatile memory bank uses doped polysilicon to make a floating gate (floating gate, FG) and a control gate (control gate, CG). Furthermore, a gate dielectric layer is used to separate the floating gate from the control gate, and a tunnel dielectric layer is used to separate the floating gate from the substrate. Whe...
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IPC IPC(8): H01L21/28H01L21/336H01L21/8247H01L29/423H01L29/788H01L27/115H10B69/00
Inventor 张格荥张骕远
Owner POWERCHIP SEMICON CORP