Method and structure for reducing floating body effects in mosfet devices

Abstract

A field effect transistor (FET) device includes a body substrate, a gate insulating layer formed over the body substrate, a source formed in an active device region associated with the body substrate, and a gate insulating layer formed over the body substrate. a drain region, each of said source and drain regions defining a p / n junction with respect to a body region of said active device region, and a junction formed within a cavity defined in said source region across said The p / n junction of the source region and into a conductive plug in the body region, wherein the conductive plug facilitates a discharge path between the body region and the source region.

Description

technical field [0001] The present invention relates generally to semiconductor device processing techniques and, more particularly, to a method and structure for reducing floating body effects in metal oxide semiconductor field effect transistor (MOSFET) devices, including silicon-on-insulator (SOI) devices . Background technique [0002] Demands for increased performance, functionality, and manufacturing economics of integrated circuits have led to enormous integration densities in order to reduce signal propagation times and increase noise immunity, while also increasing the number of chips that can be formed on a chip or wafer by a single process sequence. Number of circuits and components. Scaling devices to such small dimensions limits operating margins and necessitates increased uniformity in the electrical characteristics of semiconductor devices formed on a chip. [0003] To meet the latter criteria, silicon-on-insulator (SOI) wafers are used to take advantage of ...

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Problems solved by technology

Unfortunately, as opposed to source diode leakage in switching devices, drain diode leakage increases the thermal power dissipated in the circuit and reduces the actual switching current, resulting in lower speed

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