Peripheral unit interconnection high speed bus interface and switchboard port testing method and system

Abstract

The invention relates to a PCIe bus interface bandwidth test method, comprising the followings steps that: the data received by an Ethernet test device line speed is stored into a second memory module by a first network interface module through a first PCIe bus interface and a second PCIe bus interface, or the data in the second memory module is sent out by the first network module through the first network module; a first CPU calculates the data volume received from the Ethernet test device line speed by the first network interface module per unit time or the data volume sent by the first network interface module line speed. The invention also provides a PCIe bus interface performance test method and a PCIe exchange port bandwidth and performance test method. The method provided by the invention overcomes the shortcomings of the prior art and realizes the adoption of the Ethernet test device to test the PCIe bus interface and the bandwidth and performance of the PCIe exchange port.

Description

technical field [0001] The invention relates to a method for testing a bus interface, in particular to a method and system for testing the bandwidth and performance of an interconnected bus interface of external equipment and a port of a switch by using Ethernet network testing equipment. Background technique [0002] The Peripheral Component Interconnect Express (PCIe) bus is a type of Peripheral Component Interconnect (PCI) bus. The PCIe bus follows the existing PCI bus programming concepts and communication standards, and only needs to modify the physical layer to convert an existing PCI system to a PCIe system without requiring software modifications. The PCIe bus replaces the parallel physical layer signal of the PCI bus with a separate serial physical layer for sending and receiving. The PCIE bus has a faster rate and can replace almost all existing internal buses. The data transmission on the PCIe bus is based on the packet (Packet). The minimum length of the packet ...

AI Technical Summary

Problems solved by technology

In the DMA mode, each PCIe data packet with random content and length needs to be generated by the CPU. Due to the limited computing power of the CPU, the data flow transmitted on the PCIe interface cannot reach its maximum bandwidth in this case, so it cannot be detected. Reliability and stability of PCIe interface

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