Under bump metallurgy structure of a package and method of making same
A technology of under-bump metal layer and metallization structure, which is applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device parts, semiconductor devices, etc., and can solve problems such as metal connection and metal cracking
Inactive Publication Date: 2008-08-13
SILICON STORAGE TECHNOLOGY +1
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Problems solved by technology
A disadvantage of the structure shown in Figure 2 is that the sputtered layers 206 / 205 are typically very thin and can cause problems with metal-to-metal connections
Also, the solder ball stress hits the aluminum pad without any buffer
Thus, during temperature cycling, the metal may crack
Method used
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[0015] The invention discloses an under-bump metal layer structure for semiconductor packaging of bare chips and a preparation method thereof. It can also be applied to wafer level packaging. Some example embodiments of the present invention will now be described in more detail. It should be recognized, however, that the invention is capable of wide application in other embodiments than those expressly described, and that the scope of the invention is not limited to the disclosure, except as specified in the appended claims.
[0016] A new under bump metallization (UBM) layer is disclosed herein that is particularly suitable for use with wafer level chip scale packaging (WLCSP). The UBM significantly increases the lifetime of the package and also avoids tin penetration problems. The mechanical properties of the solder joint are further enhanced by providing a larger contact area between the material of the UBM and the flux material, thus increasing the integrity of the flux ...
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A package for a semiconductor integrated circuit die comprises a redistributed layer formed over a first barrier layer electrically connected to a bonding pad of a die. A second barrier layer is formed over the redistributed layer. A multi-metal layer is formed over the second barrier layer for coupling to a solder ball, wherein the multi-metal layer has an extending part that extends outside a second opening over the upper of the second dielectric layer to prevent tin infiltration from the solder ball to the redistribution layer.
Description
technical field [0001] The present invention relates to under bump metallurgy (UBM) structures in semiconductor packages, and more particularly, to UBM schemes to prevent tin penetration. Background technique [0002] As integrated circuits (ICs) move toward higher speeds and larger pin counts, conventional techniques for implementing fine pitch wire bonding structures cannot be used as conventional wire bonding techniques have approached or even reached their limits. Keeping pace with demands created by increased IC chip processing speeds and higher IC chip pin counts. Likewise, the current trend is to replace wire bond structures with other packaging structures and components, such as flip chip packages and wafer level packages (WLP). [0003] Some die-bonding techniques utilize copper bumps attached to pads on the die to establish electrical connections for signal input and output. For example, new packaging methods include BGA (ball grid array) and CSP (chip scale pack...
Claims
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IPC IPC(8): H01L23/485H01L21/60
CPCH01L2224/03828H01L2224/05171H01L2924/0105H01L2224/05624H01L2224/05155H01L2924/01022H01L2224/05111H01L2224/0401H01L2224/1147H01L2924/01028H01L2224/02331H01L2224/0347H01L2924/01013H01L2224/0508H01L2924/01033H01L2924/01074H01L2224/05022H01L2924/01078H01L2924/01073H01L2924/01051H01L2924/01015H01L2924/01082H01L2924/01004H01L24/13H01L2224/05027H01L2924/01322H01L2924/01327H01L2924/01029H01L2924/00013H01L2224/11849H01L2224/05008H01L2224/05139H01L2924/014H01L2924/01024H01L2224/05572H01L2224/05644H01L2924/01047H01L2924/05042H01L2224/11334H01L2924/01079H01L2224/1132H01L24/05H01L24/03H01L2924/14H01L2224/05584H01L2224/03462H01L2924/01006H01L2224/05083H01L2924/01014H01L2924/01075H01L2224/05147H01L2924/3025H01L2224/13111H01L2924/0002H01L2924/00014H01L2224/13099H01L2224/05099H01L2224/13599H01L2224/05599H01L2224/29099H01L2224/29599H01L2224/05552
Inventor S·房W·K·杨C·L·蔡
Owner SILICON STORAGE TECHNOLOGY