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Package structure to improve the reliability for WLP

A packaging structure and reliability technology, applied to electrical components, electrical solid devices, circuits, etc., can solve problems such as deformation or cracking, packaging failure, etc.

Inactive Publication Date: 2008-09-03
ADVANCED CHIP ENG TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The high stress of the bonding material during the cooling process may cause it to deform or crack, resulting in package malfunction

Method used

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  • Package structure to improve the reliability for WLP
  • Package structure to improve the reliability for WLP

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Embodiment Construction

[0031] The present invention will be described in detail with preferred embodiments and viewpoints, and such descriptions are to explain the structure and procedures of the present invention, and are only used for illustration and not for limiting the scope of claims of the present invention. Therefore, besides the preferred embodiment in the description, the present invention can also be widely practiced in other embodiments.

[0032] In general, the so-called one embodiment or an embodiment in this specification refers to describing a special feature, structure or characteristic in its connection relationship, and is included in at least one implementation of the present invention. Therefore, an embodiment or an embodiment appearing in each embodiment in the whole description need not be specified as the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner within one or more embodiments.

[0033] The ma...

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Abstract

The present invention provides a package structure to improve the reliability for WLP (Wafer Level Package). The package structure includes at least two areas. One area is harder than another. The hard area sustains more shears resulting from board drop test than the soft area in order to disperse the shear in the soft area to avoid the peeling of the buffer layers within the soft area.

Description

technical field [0001] The present invention relates to a packaging structure, in particular to a packaging structure for improving the reliability of silicon wafer level packaging (WLP). Background technique [0002] In semiconductor device assembly, a semiconductor chip (also referred to as an integrated circuit chip or "die") can be attached to a package substrate without the need for lead frames or wire bonds. These chips are formed into spherical particles or solder bumps to attach to the I / O solder pads. [0003] In conventional packaging methods, a semiconductor die and a packaging substrate are connected and mechanically fixed through a solder joining operation. The die is aligned and placed on a substrate so that the solder balls of the die are aligned with electrical pads or pre-soldered on the substrate. The substrate is generally composed of organic material or laminate, which is heated to form an alloy, and an electrical connection is formed between the die a...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/31H01L23/29
CPCH01L2924/14H01L2924/15311H01L23/49894H01L23/49816H01L24/16H01L2224/0557H01L2224/05573H01L2224/056H01L2224/05571H01L2924/00014H01L2224/0554H01L2224/06131H01L2224/05599H01L2224/0555H01L2224/0556
Inventor 杨文焜林殿方
Owner ADVANCED CHIP ENG TECH INC