Programmable on-chip memorizer interface NOR flash memory reading quickening control method

Abstract

The invention discloses an accelerating control method for the NOR flash memory read of the memory interface on a programmable chip belonging to an embedded memory technology field, first, in an objective program instruction needed in the executing of the NOR flash memory, configuring the interface of the NOR flash memory and the memory on chip according to the address space of the objective program in the NOR flash memory; then, reading the objective program instruction in the NOR flash memory and sending the read objective program instruction to the on chip memory through the interface whenexecuting the objective program first time; the system reads the objective program instruction in the memory on chip directly and executes in the following course of executing the objective program, instead of reading the objective program instruction in the NOR flash memory, when the system executes other instructions, the system reads the instruction in the NOR flash memory and executes still. The invention increases the read speed, and can support the on chip memory with different sizes through hardware interface programming, avoided the problem of compatibility.

Description

technical field [0001] The invention relates to a method for controlling a memory interface in the technical field of electronic engineering, in particular to a control method for reading a NOR flash memory with a memory interface on a programmable chip. Background technique [0002] NOR (or not) flash memory is widely used in system-on-chip and handheld mobile devices. However, the read time required by NOR flash memory is still too slow compared to the clock frequency of system-on-chip and handheld mobile devices. There have been many studies on NOR flash reading acceleration in the past, such as history buffer, pre-reading, and multi-block flash memory parallel reading mechanism. From the perspective of hardware, the reading speed has been continuously improved, but for NOR flash reading acceleration Most of the research on speed improvement is limited or the cost is too high, and there are not many studies on improving NOR flash memory from the perspective of software a...

AI Technical Summary

Problems solved by technology

However, the disadvantage of this method is that the on-chip memory requires a relatively complex allocation strategy to select appropriate data, which increases the workload of the software part in the software-hardware co-design to a certain extent. For different applications, different allocation strategies are required. Reduced ease of design, which is unacceptable in practical applications

Images