CMOS structure and its making method

Abstract

The method relates to a CMOS structure and a manufacturing method. The CMOS structure includes an n-FET device comprising an n-FET channel region and a p-FET device comprising a p-FET channel region. The n-FET channel region includes a first silicon material layer located upon a silicon-germanium alloy material layer. The p-FET channel includes a second silicon material layer located upon a silicon-germanium-carbon alloy material layer. The silicon-germanium alloy material layer induces a desirable tensile strain within the n-FET channel. The silicon-germanium-carbon alloy material layer suppresses an undesirable tensile strain within the p-FET channel region. A silicon-germanium-carbon alloy material from which is comprised the silicon-germanium-carbon alloy material layer may be formed by selectively incorporating carbon into a silicon-germanium alloy material from which is formed the silicon-germanium alloy material layer.

Description

technical field [0001] The present invention generally relates to complementary metal oxide semiconductor (CMOS) structures. More specifically, the present invention relates to CMOS structures with enhanced performance. Background technique [0002] In semiconductor circuits, field effect transistors (FETs) are generally used as switching devices or signal processing devices. To reduce power consumption, it is usually fabricated as a pair of field effect transistors that are complementary doped (that is, include n-conductivity-type dopants and p-conductivity-type dopants) typically referred to as Complementary Metal-Oxide-Semiconductor (CMOS) structures field effect transistor. [0003] New developments in field effect transistor structures and device fabrication have focused on the use of mechanical stress layers within field effect transistor structures in order to provide mechanically strained channel regions within field effect transistor structures. In turn, a mechan...

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Problems solved by technology

However, it is often difficult to effectively achieve such different stress and strain levels in n-FET and p-FET channels when designing and fabricating CMOS structures

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