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Semiconductor device and production method thereof

A manufacturing method and semiconductor technology, applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve the problems of difficulty in ensuring the reliability of the package, brittleness and damage of weak low-k materials, and achieve Stress reduction effect

Inactive Publication Date: 2009-03-18
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In this way, in semiconductor devices using low-k materials and Pb-free solder balls, due to the residual stress in the solder balls generated during mounting and the thermal stress generated during use, breakage of the connection portion containing solder balls may occur. Or the brittle damage, peeling and cracking of low-k materials with weak mechanical strength may make it difficult to ensure the reliability of the package during assembly or practical use

Method used

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  • Semiconductor device and production method thereof
  • Semiconductor device and production method thereof
  • Semiconductor device and production method thereof

Examples

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Embodiment 1

[0072] A semiconductor device according to Embodiment 1 of the present invention will be described using the drawings. figure 1 It is a partial cross-sectional view schematically showing the configuration of the semiconductor device according to Embodiment 1 of the present invention. figure 2 It is an enlarged partial cross-sectional view schematically showing the configuration of the first wiring structure in the semiconductor device according to the first embodiment of the present invention.

[0073] refer to figure 1 , in the semiconductor device according to the first embodiment, the semiconductor substrate 11 is provided, and the first wiring structure 12 is provided on the surface of the semiconductor substrate 11 . The second wiring structure 17 is provided on the first wiring structure 12 . The semiconductor substrate 11 is made of, for example, Si or GaAs.

[0074] refer to figure 2 , in the first wiring structure 12, diffusion layers 22, 23 (for example, a sour...

Embodiment 2

[0113] A semiconductor device according to Embodiment 2 of the present invention will be described with reference to the drawings. Figure 9 It is a partial cross-sectional view schematically showing the configuration of a semiconductor device according to Embodiment 2 of the present invention.

[0114] In the semiconductor device according to the second embodiment, the third via 19 electrically connecting the first wiring structure 12 and the second wiring structure 17 provided on the passivation film 13 has a larger diameter than the second via 16. Taper angle, this point and embodiment 1 (with reference to figure 1 ) involves different semiconductor devices. Other constitutions are the same as in Embodiment 1. in addition, Figure 9 The external terminal 18 is constructed with figure 1 The same composition can also be Figure 4 , 5 Same construction. Moreover, it also has Image 6 The effect of reducing the number of external terminals 18 related to the integration ...

Embodiment 3

[0125] A semiconductor device according to Embodiment 3 of the present invention will be described with reference to the drawings. Figure 10 It is a partial cross-sectional view schematically showing the configuration of a semiconductor device according to Embodiment 3 of the present invention.

[0126] The semiconductor device related to Embodiment 3 is the same as that of Embodiment 1 (refer to figure 1 ) and Example 2 (see Figure 9 ) compared with the semiconductor device involved, the third via 19 electrically connecting the first wiring structure 12 and the second wiring structure 17 on the passivation film 13 is provided separately from the second wiring layer 15. The second wiring layer 15 is different in that there is an adhesive layer 37 therebetween. Other constitutions are the same as in Embodiment 1. in addition, Figure 10 The external terminal 18 is constructed with figure 1 The same composition can also be Figure 4 , 5 Same construction. Moreover, it ...

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Abstract

A highly reliable semiconductor device in which connection reliability is assured at very small vias comprises: a semiconductor substrate (11); a first wiring structure (12) placed on the semiconductor substrate (11) and having one or more first wiring layers, one or more insulating layers and a first via; a second wiring structure (17) placed on the first wiring structure (12) and having one or more second wiring layers (15), one or more second insulating layers (14), a second via (16) and a third via (19); and an external terminal (18) provided on the second wiring structure (17). The second via (16), which is connected to the second wiring layer (15) of the second wiring structure (17) and to the external terminal (18), has a connection interface (16a) disposed at an end of the via (16) that is on the side of the external terminal (18).

Description

technical field [0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a highly reliable semiconductor device in a package state in which a semiconductor device is connected to a mounting substrate and a manufacturing method thereof. Background technique [0002] In recent years, along with miniaturization and higher functionality of electronic equipment, miniaturization and higher density of wiring are also required for semiconductor chips. For example, in a microprocessor designed according to the 90nm rule, its clock frequency reaches several GHz, and the drive current reaches 100A, and the performance improvement of the previous wiring technology is reaching the limit. In order to realize a microprocessor with a clock frequency exceeding 10 GHz and a drive current of hundreds of A, a completely new structure of wiring technology is required. In particular, for semiconductor chips operating at high spee...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/485H01L21/60
CPCH01L23/53238H01L2924/19043H01L2924/3011H01L2924/01079H01L2924/30105H01L2924/14H01L23/5283H01L24/05H01L2924/01019H01L2924/19042H01L2924/01322H01L2924/00013H01L23/53223H01L2924/01078H01L2924/01057H01L2924/19041H01L2924/30107H01L2924/12044H01L23/5329H01L2924/13091H01L2224/29099H01L2924/00
Inventor 菊池克山道新太郎川野连也副岛康志
Owner RENESAS ELECTRONICS CORP