Semiconductor Package Substrate Structure
A technology for packaging substrates and semiconductors, which is applied in semiconductor devices, semiconductor/solid-state device parts, electric solid-state devices, etc., can solve problems such as bad, easy-to-produce offset electrical connections, etc., and achieve the effect of ensuring quality and reliability
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
no. 1 example
[0057] see Figure 4A to Figure 4I ’ is a schematic cross-sectional view showing the manufacturing method of the first embodiment of the semiconductor package substrate structure of the present invention.
[0058] like Figure 4A As shown, a circuit board 40 is first provided, and a conductive layer 41 is formed on the surface of the circuit board 40. The material of the conductive layer 41 can be selected from the group consisting of copper, tin, nickel, chromium, titanium and copper-chromium alloy One of them, or the material of the conductive layer 41 is a conductive polymer, and the conductive layer is preferably copper foil or electroless copper plating.
[0059] like Figure 4B As shown, a first resistance layer 42 is formed on the surface of the conductive layer 41 which is a dry film or liquid photoresist, and the first resistance layer 42 is formed with an opening 420 to expose part of the conductive layer 41 .
[0060] like Figure 4C As shown, at least one first...
no. 2 example
[0071] see Figure 5A to Figure 5I ’, is a schematic cross-sectional view showing the manufacturing method of the second embodiment of the semiconductor package substrate structure of the present invention.
[0072] This example Figure 5A to Figure 5I ’ process steps and structure, of which Figure 5A to Figure 5C is the same as the first embodiment Figure 4A to Figure 4C The recipe shown is the same; however, as Figure 5D The ones shown in the following are different, and a second resistance layer 44 is formed on the surface of the first resistance layer 42, the first electrical connection pad 43a and the circuit 43b, which is a dry film or liquid photoresist, and the second resistance layer 44 An opening 440 is formed to expose the first electrical connection pad 43a, wherein the second resistance layer opening 440 exposes part of the upper surface of the first electrical connection pad 43a; Figure 5E to Figure 5G As shown, the conductive column 45 is formed by elect...
no. 3 example
[0074] see Figure 6A to Figure 6I , is a schematic cross-sectional view showing the manufacturing method of the third embodiment of the semiconductor packaging substrate structure of the present invention; the difference from the first and second embodiments is that the surface of the circuit board has first and second electrical connection pads and circuits.
[0075] like Figure 6A As shown, firstly, a circuit board 40 is provided, and a conductive layer 41 is formed on the surface of the circuit board 40 .
[0076] like Figure 6B As shown, a first resistance layer 42 is formed on the surface of the conductive layer 41 , and the first resistance layer 42 is formed with an opening 420 to expose part of the conductive layer 41 .
[0077] like Figure 6CAs shown, the conductive layer 41 is used as a current conduction path for electroplating, so that at least one first electrical connection pad 43a, a circuit 43b and a second electrical connection are formed on the surface...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More