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Method, system, and computer program product for generating automated assumption for compositional verification

A computer, finite automaton technology, applied in computer-aided design, computing, instrumentation, etc., that can solve problems such as no approximate boundaries

Inactive Publication Date: 2009-04-08
CADENCE DESIGN SYST INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, the main drawback of this approach is that there is no approximate bound

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  • Method, system, and computer program product for generating automated assumption for compositional verification
  • Method, system, and computer program product for generating automated assumption for compositional verification
  • Method, system, and computer program product for generating automated assumption for compositional verification

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Embodiment Construction

[0022] Several embodiments of the invention provide methods, systems and computer program products for generating automated hypotheses for combinatorial verification. see Figure 1A , at 152, the process begins by identifying a first set and a second set of behaviors of the electronic circuit design. The identified data will be used to characterize the design of the system (whether electronic hardware, software, or a combination of hardware and software) as a "finite automaton" (also known as a finite state machine) composed of A model of behavior composed of a finite number of states, transitions between those states, and operations.

[0023] Next, at 154, the process iteratively computes a smallest "Incomplete Deterministic Finite Automata" (IDFA) based on sampling the first and second sets of behaviors. A deterministic finite state machine is one that has one and only one transition to the next state for each pair of state and input symbol. In some cases, a finite state a...

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Abstract

Disclosed are methods, systems, and computer program products for computing an exact minimal automaton to act as an intermediate assertion in assume-guarantee reasoning. In one embodiment, the computing an exact minimal automaton is performed by using a sampling approach and a Boolean satisfiability, The methods described herein may be used as part of a tool for formal verification.

Description

Background technique [0001] In the context of hardware and software systems, software testing has been widely used to debug a system or demonstrate that the system exhibits certain characteristics. However, software testing by itself often cannot prove that a system is free of specific types of defects. And it cannot, by itself, demonstrate that a system exhibits a particular characteristic. Formal verification, on the other hand, enables the use of mathematical methods to adequately prove or disprove the correctness of software and hardware systems, thereby proving that the system of interest does not have certain defects, or exhibit certain properties. [0002] More specifically, by using abstract mathematical models, formal verification attempts to prove that a system of interest satisfies certain requirements, or that said system is capable of exhibiting certain properties or behaviors. That is, formal verification of such systems is performed by providing formal proofs ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F17/504G06F30/3323
Inventor A·格普塔K·L·麦克米伦
Owner CADENCE DESIGN SYST INC
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