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Active element array substrate

An array substrate and active element technology, which is applied in the field of active element array substrates, can solve the problem that the connection conductor 120 cannot be blown out effectively, and achieve the effect of reducing line defects

Active Publication Date: 2009-05-20
AU OPTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, from Figure 1B In the equivalent circuit judgment, the first data line DL1, the second data line DL2 and the third data line DL3 with branch design will still have a large current test signal through, so the first data line DL1, the second The branch design of the first data line DL2 and the third data line DL3 cannot effectively improve the situation that the connecting conductor 120 is blown during the test, and the situation that the connecting conductor 120 is blown during the test is still serious, such as Figure 2A and Figure 2B indicated by the circle in the

Method used

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  • Active element array substrate
  • Active element array substrate
  • Active element array substrate

Examples

Experimental program
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no. 1 example

[0060] FIG. 3 is a schematic diagram of an active device array substrate in an embodiment of the present invention. Please refer to FIG. 3. The active device array substrate 200 of this embodiment includes a substrate 210, a pixel array 220 and a peripheral circuit 230. The substrate 210 has a display area 212 and a peripheral area 214. The pixel array 220 is disposed on the display area 212 of the substrate 210. The pixel array 220 includes a plurality of signal lines 222 and a plurality of pixels 224, and each pixel 224 is associated with a corresponding signal. The lines 222 are electrically connected, and each signal line 222 extends from the display area 212 to the peripheral area 214 respectively. The peripheral circuit 230 is disposed on the peripheral area 214, and the peripheral circuit 230 has a test circuit 232 electrically connected to the signal line 222. In this embodiment, the peripheral circuit 230 generally refers to a circuit design disposed on the peripheral are...

no. 2 example

[0068] Fig. 5A is a top view of the test circuit in the second embodiment of the present invention, and Fig. 5B is an equivalent circuit diagram of the test circuit in Fig. 5A. Please refer to FIG. 4A, FIG. 5A and FIG. 5B at the same time. The test circuit 232a of this embodiment is similar to the test circuit 232 of the first embodiment, and the similar description is omitted here. Please refer to the description of the first embodiment. The main difference between the two is: in the test line 232a of this embodiment, the first data line DL1, the fourth data line DL4, and the seventh data line DL7 pass through the leftmost first connecting conductor C1' Are electrically connected to each other, the second data line DL2, the fifth data line DL5, and the eighth data line DL8 are electrically connected to each other through the leftmost second connecting conductor C2', and the third data line DL3, The sixth data line DL6 and the ninth data line DL9 are electrically connected to each...

no. 3 example

[0071] Fig. 6A is a top view of the test circuit in the third embodiment of the present invention, and Fig. 6B is an equivalent circuit diagram of the test circuit in Fig. 6A. 6A and 6B, in the test circuit 232b of this embodiment, the number of connecting conductors C across the two data lines DL is more than that of the first and second embodiments, and similar descriptions please Check the first embodiment or the second embodiment, which will not be described here. In this embodiment, each of the first connecting conductor 1, the second connecting conductor C2, and the third connecting conductor C3 span two Between the data lines DL and electrically connected to the two data lines DL.

[0072] It can be seen from this embodiment that the present invention can make an appropriate number (part or all) of the first connecting conductor C1, the first connecting conductor C2, and the first connecting conductor C3 span two or more data according to actual design requirements. On the ...

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Abstract

The invention provides an active element array baseplate which comprises a baseplate, a pixel array and a peripheral circuit. The baseplate is provided with a display region and a peripheral region; the pixel array is arranged on the display region of the baseplate; the pixel array comprises a plurality of signal lines and a plurality of pixels; each pixel is respectively in electric connection with the corresponding signal line; and each signal line respectively extends from the display region to the peripheral region. The peripheral circuit is arranged on the peripheral region; and the peripheral circuit is provided with a testing circuit in electric connection with the signal line. In addition, the testing circuit comprises a plurality of short circuit rods and a plurality of connecting conductors; each signal line is respectively connected with one of the short circuit rods through one of the connecting conductors; at least two signal lines connected with the same short circuit rod are in electric connection through one of the connecting conductors. The active element array baseplate is uneasy to have the problem of circuit opening between the signal line and the short circuit rod and can effectively reduce the probability of line defect.

Description

Technical field [0001] The present invention relates to an active device array substrate, and more particularly to an active device array substrate that can effectively prevent signal lines from being opened during testing. Background technique [0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) with superior characteristics such as high image quality, good space utilization efficiency, low power consumption, and no radiation has gradually become the mainstream of displays. During the manufacturing process of the liquid crystal display panel, it needs to be tested to confirm that the manufactured liquid crystal display panel can operate normally. Generally speaking, manufacturers will use a shorting bar design to test liquid crystal display panels. In detail, when the liquid crystal display panel is tested, a gate test signal is applied to all the scan lines at the same time through a gate shorting bar connected to the scan lines, so that all pixels are at the same tim...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G02F1/1362G02F1/13G01R31/00
Inventor 李仁杰冯顺发
Owner AU OPTRONICS CORP