Delay locked loop circuit and method for eliminating jitter and offset therein

Abstract

A delay locked loop (DLL) circuit is provided. The DLL circuit includes a divider, a shift register, a digital-to-analog converter and a voltage controlled delay line. The divider divides an input clock signal to output a reference clock signal. The shift register is triggered by the reference clock signal and outputs a digital signal corresponding to the reference clock signal in accordance with a phase difference between the input clock signal and a feedback clock signal. The digital-to-analog converter transfers the digital signal output from the shift register into a control voltage. The voltage controlled delay line outputs the feedback clock signal in accordance with the control voltage transferred by the digital-to-analog converter. A method for eliminating jitter and offset between an input clock signal and an output clock signal in a delay locked loop circuit is also disclosed.

Description

technical field [0001] The present invention relates to a clock synchronization circuit, and more particularly to a delay locked loop (DLL) circuit and a method for eliminating jitter and skew between signals therein. Background technique [0002] In general electronic devices or systems, a clock synchronization circuit is usually used to provide a stable and good clock signal, so that the electronic products can exhibit better overall performance. The above-mentioned clock synchronization circuit includes a phase locked loop (PLL) circuit and a delay locked loop (DLL) circuit, both of which conceptually operate in a similar manner. For the DLL circuit, it includes analog and digital DLL circuits, and the two have different performances according to different requirements. [0003] FIG. 1 is a schematic diagram showing a general analog delay locked loop circuit. The analog delay-locked loop circuit 100 includes: a phase-frequency detector (phase-frequency detector) 102, a ...

AI Technical Summary

Problems solved by technology

However, in a combined DLL circuit, the frequency of the digital part is higher than that of the analog part, so the combined DLL circuit cannot operate as stably as an analog or digital DLL circuit

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