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Heterogeneous Processors Sharing a Common Cache

一种异构处理器、高速缓存的技术，应用在处理器领域

Inactive Publication Date: 2012-02-22
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

A cache (typically based on static random-access memory, or "SRAM") can return data faster than main memory, but uses more area and power

Method used

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  • Heterogeneous Processors Sharing a Common Cache
  • Heterogeneous Processors Sharing a Common Cache
  • Heterogeneous Processors Sharing a Common Cache

Examples

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Embodiment Construction

[0054] Figures 1A-1CA multiprocessor system 10 is shown including a multiprocessor 12 coupled to main memory 14 by a memory bus 16 . The multiprocessor 12 includes a cache (“shared cache”) 18 and a plurality of processor “cores” (collectively processor cores 20 ) that are connected to and share the cache 18 . Shared cache 18 in this figure is intended to represent a unit comprising cache memory and associated control logic. Cache control logic includes logic for mapping memory addresses ("cache tags") that are currently cached with their associated cache lines.

[0055] The processor core 20 includes heterogeneous cores, that is, processor cores (or types of processor cores) with different structures. For example, processor core 20 may include one or more special purpose processor cores and / or at least one central processing unit (CPU) core.

[0056] Special purpose processor cores may include, for example, at least one network processor unit (NPU) core and / or a graphics en...

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PUM

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Abstract

A multi-core processor providing heterogeneous processor cores and a shared cache is presented.

Description

[0001] This application is a divisional application of the following application. The filing date of the original application is November 18, 2005. The title of the invention is "Heterogeneous Processor Sharing Common Cache", and the application number is 200510023015.0. technical field [0002] The invention relates to a processor, in particular to a heterogeneous processor sharing a common cache. Background technique [0003] Modern general-purpose processors typically access main memory (typically implemented as dynamic random access memory, or "DRAM") through a hierarchy of one or more caches (eg, L1 and L2 caches). A cache (typically based on static random access memory, or "SRAM") can return data faster than main memory, but uses more area and power. Memories accessed by general-purpose processors typically exhibit high temporal and spatial locality. A cache takes advantage of this by fetching data from main memory in larger chunks than needed (spatial locality) and k...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/78
CPCG06F12/084G06F15/167G06F15/7842G06F15/781G06F13/4022G06F13/4282G06F15/7846G06F2212/302G06F12/0815G06F12/0893G06F2212/621G06F12/0811G06F2212/283G06F2212/314
Inventor F·哈迪M·卡波特J·贝克M·罗森布卢特
Owner INTEL CORP