Capacitance arrangement and method relating thereto

Abstract

The present invention relates to a capacitance arrangement (10) comprising at least one parallel-plate capacitor comprising a first electrode means, a dielectric layer and a second electrode means partly overlapping each other, the equivalent capacitance of being dependent on the size of the overlapping area. A misalignment limit (delta xA) is given. Said first electrode means comprises a first and a second electrode (41,42) arranged symmetrically with respect to a longitudinal axis (x) , said first and second electrodes have a respective first edge, which face each other, are linear and parallel such that a gap is defined there between. Said second electrode means (3) comprises a third electrode with a first section (31) and a second section (32) disposed on opposite sides of said gap interconnected by means of an intermediate section (33), which is delimited by a function F(x) depending on a first parameter k and a second parameter A. One of said two parameters is adapted to be selected hence allowing calculation of the other parameter to determine the shape and size of the second electrode means such that the capacitance of the capacitance arrangement will be misalignment invariable within the misalignment limit.

Description

technical field [0001] The invention relates to a capacitive arrangement consisting of at least one parallel-plate capacitor comprising a first electrode part, a dielectric layer and a second electrode part, which are arranged substantially parallel on both sides of said dielectric layer and mutually partial overlap, whereby the equivalent capacitance depends on the size of the overlapping area (overlapping area) of said first and second electrode parts, and wherein a misalignment limit is given which defines the corresponding first and second electrode parts The maximum tolerable degree of misalignment between the second electrode parts. The invention also relates to a method of manufacturing such a capacitive device. Background technique [0002] It is a well-known fact that it is very difficult or even impossible to manufacture capacitors with exactly the desired capacitance due to tolerable misalignments during the manufacturing process, especially in the case of parall...

AI Technical Summary

Problems solved by technology

like Figures 1B-1C The varactor shown with parallel plate electrodes does not require such high voltages, usually it is sufficient to have a voltage of 5-20V, but on the other hand, this design has the disadvantage that during the manufacturing process they are Sensitive to alignment of top and bottom electrodes

Normally, ferroelectric films with very high permittivity are used, and due to this very high permittivity, typically above 100, a small misalignment Δ1 (see Figure 1C ) will also result in a significant change in capacitance, which makes the prediction of capacitance uncontrollable, and thus the design of such devices is less cost-effective

Figure 1D , 1E The design shown in provides good capacitance predictions, but it requires more masks and fabrication processes, making it cost-ineffective

Figure 1F The arrangement shown in provides relatively good capacitance predictions, but it has the disadvantage that additional ohmic losses are associated with jumpers connecting the wires or pads of the capacitors in the overlap region of the parallel plate structure

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