Back-to-front via process

Abstract

A method performed on a semiconductor chip having a doped semiconductor material abutting a substrate involves creating a first via through at least a portion of the substrate extending from an outer side of the substrate towards the doped semiconductor material, the first via having a wall surface and a bottom, introducing a first electrically conductive material into the first via so as to create an electrically conductive path, creating a second via, aligned with the first via, extending from an outer surface of the doped portion of the semiconductor chip to the bottom, and introducing a second electrically conductive material into the second via so as to create an electrically conductive path.

Description

technical field [0001] The present invention relates to semiconductors, and more particularly to the electrical connection of such devices. Background technique [0002] It is very difficult to manufacture (by forming conductive vias) electrical contacts that extend all the way through the electronic chip. It is almost impossible to fabricate with high precision or controllable repeatability, let alone high volume, unless one or more of the following conditions are met: a) the channel is very shallow, i.e., the depth is significantly less than 100 microns, b) the channel width Large, or c) the channels are separated by a large pitch, ie a pitch many times the channel width. The difficulty increases when the channels are close enough for signal crosstalk to occur, or if the chip the channel penetrates is charged, since the conductors in the channel are neither allowed to act as shorts nor carry a different charge than the corresponding parts of the chip. In addition, conven...

AI Technical Summary

Problems solved by technology

[0003] Indeed, there are still many problems in the field of semiconductor technology. These problems include: using large-scale disproportionate packages; assembly costs are not proportional to semiconductors; A small part of the chip area really needs a high-performance process; the current process is limited by voltage and other technologies; chip designers are limited to one design process and one design material; chip-to-chip (through packaging) connections require large size and high power pad drivers; even a small change or correction of a tiny design error requires the fabrication of one or more new masks for an entire new chip; mask costs alone are millions of dollars to manufacture an entire new chip; testing of individual chips is difficult and complex, and chip combinations are even more difficult to test before they are packaged

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