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Image processing apparatus

An image processing device and image processing technology, applied in the direction of image communication, TV, color TV components, etc., can solve the problems of external interface and memory bus electrical design difficulties, etc., to achieve effective utilization, effective bandwidth, and reduced access number Effect

Inactive Publication Date: 2009-12-02
HITACHI LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this publication, it is stated that "[the problem] is that it is necessary to increase the data bandwidth at the time of memory access, and on the other hand, it is faced with the difficulty in the electrical design of the external interface of the memory LSI and the speed-up of the memory bus.

Method used

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Experimental program
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Embodiment 1

[0039] The configuration and operation of an image processing device as a preferred embodiment of the present invention will be described.

[0040] use figure 1 The configuration of the embodiment will be described.

[0041] figure 1 The image processing units 001, 004, 007, and 010 are, for example, to process baseband signals such as luminance signals and color difference signals quantized to 8 bits as image data in units of frames, for example, it is necessary to write or read SDRAM The above-mentioned baseband signal is input to the compression unit 003,009 through the input unit 002,008.

[0042]Also, the baseband signals subjected to expansion processing by the expansion units 006 and 012 are supplied to the image processing units 004 and 010 via the output units 005 and 011 . The compression units 003 , 009 and the expansion units 006 , 009 perform write or read processing on the external memory 16 connected to the connection unit 015 via the memory control unit 014 ...

Embodiment 2

[0072] Figure 11 This is an embodiment of an image processing unit.

[0073]Parts having the same functions are assigned the same reference numerals and related explanations are omitted.

[0074] The first image processing unit 020 is, for example, a noise removal circuit, writes input image data into the memory 016, and removes noise components using frame correlation.

[0075] Next, the encoder 024 is provided as the second image processing unit, and the noise-removed image data is written into the memory 016 , and the image data is sequentially read from the memory 016 for encoding processing to generate encoded data.

[0076] The decoder 026 is configured as a third image processing to decode the encoded encoded data into image data.

[0077] As the fourth image processing, the decoded image data is, for example, reduced to a thumbnail screen and pasted.

[0078] In a system that performs such processing, since compression and expansion units 021 and 025 perform compre...

Embodiment 3

[0082] Figure 12 Represents an embodiment applicable to an external bus such as a PCI bus instead of an external memory such as SDRAM. Parts having the same functions are assigned the same reference numerals and related explanations are omitted.

[0083] Instead of the memory control unit 014 connected to the arbitration unit 013 , an external bus control unit 030 is used and connected to the external bus 032 via a connection unit 031 . According to the above configuration, the number of times of access can be similarly reduced in PCI buses other than memory such as SDRAM.

[0084] Therefore, by creating a margin in data communication with the image processing unit 033 connected to the external bus 032 , it is possible to communicate a larger amount of information.

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PUM

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Abstract

The invention provides an image processing apparatus which is configured to have units for compressing and expanding image data and an arbitrating unit for arbitrating control units for executing image processing so that the compressing and expanding units are located between the arbitrating unit and the control units respectively. The apparatus further includes the circuits for compressing and expanding the image data in a reversible manner and a nonreversible manner so that the compressing and expanding manner may be switched according to the image processing condition. When treating a large amount of image data, this configuration enables the apparatus possible to reduce the number of accesses to memory and make effective use of a bandwidth, thereby being able to reduce the power consumption. Since the bandwidth is reduced and the random access to memory is made possible, more image processing capabilities may be provided so that the operability of this apparatus is enhanced.

Description

technical field [0001] The present invention relates to an image processing device, for example, an image processing system for processing that requires access to a memory represented by a dynamic random access memory (DRAM), such as a moving image or a still image. Background technique [0002] As background art in this technical field, there is, for example, Japanese Patent Application Laid-Open No. 10-301841 (Patent Document 1). In this publication, it is stated that “[the problem] is that it is necessary to increase the data bandwidth during memory access, and on the other hand, it faces difficulties in the electrical design of the external interface of the memory LSI and the speed-up of the memory bus. Therefore, a Memory LSI technology that realizes effective improvement of data bandwidth without relying on other methods of high-speed technology. [Solution] is a memory LSI with compression and expansion functions. Compression and expansion unit 13 is installed inside. ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04N7/26H04N5/92H04N1/46H04N1/413H04N19/00H04N19/103H04N19/134H04N19/196H04N19/423H04N19/467H04N19/50H04N19/60H04N19/61H04N19/65H04N19/70H04N19/89H04N19/90H04N19/91
CPCH04N7/26106H04N19/0049H04N7/26712H04N19/426
Inventor 野中智之小味弘典稻田圭介谷田部祐介冈田光弘
Owner HITACHI LTD