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Flotox-type eeprom

A floating gate and source technology, applied in static memory, instruments, electrical components, etc., can solve the problem of inability to reduce the unit area

Inactive Publication Date: 2009-12-02
ROHM CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This is because if a structure in which two cells are simply arranged in parallel is adopted, the cell area needs to be doubled compared with conventional EEPROMs, and even if reliability can be designed, the cell area (chip area) cannot be reduced.

Method used

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  • Flotox-type eeprom
  • Flotox-type eeprom
  • Flotox-type eeprom

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0057] Embodiments of the present invention will be described in detail below with reference to the drawings.

[0058] figure 1 It is a figure explaining the structure of the FLOTOX type EEPROM of the W cell system concerning one embodiment of this invention, (A) is a schematic top view, (B) is a cross-sectional view along b-b in (A), (C) It is a sectional view along c-c in (A).

[0059] refer to figure 1 (A) to (C), in the surface layer region of the p-type silicon substrate 21, a field (field) oxide film (LOCOS oxide film) 22 formed by the LOCOS method is formed, and the p-type silicon substrate 21 separated between elements The surface area of ​​the EEPROM forms the cell structure of the EEPROM.

[0060] The cell structure includes a cell transistor 23 and a selection transistor 24 . In the unit transistor 23, there are provided: a pair of two floating gates 25a and 25b; a control gate 26 shared by the two floating gates 25a and 25b; and a source 27 shared by the two ...

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Abstract

There has been a problem of difficult cell layout in a double-cell system FLOTOX-type EEPROM design for miniaturization. A double-cell system FLOTOX type EEPROM is provided with a pair of floating gates (25a, 25b), two tunnel windows (30a, 30b), a common source (27), a common control gate (26) and select gates (29a, 29b), and a drain (28) is shared. Thus, the double-cell system FLOTOX type EEPROM designed to have high reliability and withstand voltage is provided.

Description

technical field [0001] The present invention relates to FLOTOX (floating gate tunnel oxidation) type EEPROM (electronically erasable and programmable read-only memory), particularly relate to have paired 2 units, store the electronic erasable of the W unit mode of 1 data with 2 units Write to Programmable Read-Only Memory. Background technique [0002] The EEPROM that can be electrically written and rewritten can be rewritten on the board, and can be rewritten in units of pages or bytes. Therefore, it can be applied in a wide range. But it is necessary to design a more reliable and miniaturized EEPROM for this purpose. [0003] It has been proposed that there is such a structure for improving reliability: in a flash memory (flash), in addition to a storage unit, a verification unit is also provided for one piece of data, so that it can be easily confirmed whether it has been performed or not. Writing and erasing of data (see Patent Document 1). In the EEPROM, the W-cell ...

Claims

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Application Information

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IPC IPC(8): H01L21/8247H01L29/788H01L27/115H01L29/792G11C16/04
CPCH01L27/11524G11C16/3436H01L29/66825H01L29/42328G11C16/10H01L27/11521H01L29/7883G11C16/0433H01L21/28273H01L27/115H01L29/40114H10B41/35H10B69/00H10B41/30H10B41/10
Inventor 关口勇士
Owner ROHM CO LTD
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