Fixed-point divider and operation processing method thereof
A technology of arithmetic processing and division, applied in the direction of electrical digital data processing, digital data processing components, instruments, etc., can solve the problems of shifting and subtraction operations, etc., achieve low area and power consumption, reduce the number of cycles, high performance effect
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example 1
[0106] Example 1. In this example, assume that the division operation performed is 32-bit unsigned fixed-point division, and the dividend and divisor are 32'bit: 00000000_00000000_11111111_00000000, 32'bit: 00000000_00000000_00000000_00000000.
[0107] The specific method steps will be described below:
[0108] 11) Preprocessing stage.
[0109] Firstly, it is judged that the divisor is 0, and the division operation is an invalid operation. Therefore, the division operation enters the result processing stage.
[0110] 12) Result processing stage.
[0111] The result processing component receives the input of the 0-judgment component. Since the current division operation is an invalid operation with a divisor of 0, a series of processing measures are taken according to the design requirements (for example, a warning that the divisor is 0, etc.) is taken to complete the division operation.
example 2
[0112] Example 2. In this example, assume that the division operation performed is 32-bit unsigned fixed-point division, and the dividend and divisor are 32'bit: 00000000_00000000_11111111_00000000, and 32'bit: 00000000_00001111_00000000_00000000.
[0113] The specific algorithm steps are described below:
[0114] 21) Preprocessing stage.
[0115] Firstly, it is determined that the divisor is not 0, and the division operation is an effective operation; because the division operation is an unsigned operation, there is no need to calculate the absolute value of the dividend and the divisor; after comparison, the dividend is smaller than the divisor, so the division operation enters the result processing stage.
[0116] 22) Result processing stage.
[0117] The result processing part receives the input of the preprocessing part. Since the absolute value of the dividend is smaller than the absolute value of the divisor, the quotient value can be 0, and the remainder directly take...
example 3
[0118] Example 3. In this example, assume that the division operation performed is 32-bit unsigned fixed-point division, and the dividend and divisor are 32'bit: 00000000_00000000_11111111_00000000, 32'bit: 00000000_00000000_00000000_00001111.
[0119] According to the existing traditional division operation based on subtraction and shifting, only one bit is shifted to the left each time, and then the subtraction operation is performed. The above division operation requires 32 loop operations. The optimization of the division algorithm based on subtraction and shifting in the prior art can reduce the above operation by 16 cycles, but according to the new method proposed by the present invention, after preprocessing, only two cycles are required to complete the operation. The specific method steps will be described below:
[0120] 31) Preprocessing stage.
[0121] First, it is determined that the divisor is not 0, and the division operation is a valid operation; because the di...
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