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Fixed-point divider and operation processing method thereof

A technology of arithmetic processing and division, applied in the direction of electrical digital data processing, digital data processing components, instruments, etc., can solve the problems of shifting and subtraction operations, etc., achieve low area and power consumption, reduce the number of cycles, high performance effect

Active Publication Date: 2011-04-20
LOONGSON TECH CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] However, such optimization still does not solve the problem of too many shift and subtraction operations in the subtraction-based loop algorithm

Method used

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Examples

Experimental program
Comparison scheme
Effect test

example 1

[0106] Example 1. In this example, assume that the division operation performed is 32-bit unsigned fixed-point division, and the dividend and divisor are 32'bit: 00000000_00000000_11111111_00000000, 32'bit: 00000000_00000000_00000000_00000000.

[0107] The specific method steps will be described below:

[0108] 11) Preprocessing stage.

[0109] Firstly, it is judged that the divisor is 0, and the division operation is an invalid operation. Therefore, the division operation enters the result processing stage.

[0110] 12) Result processing stage.

[0111] The result processing component receives the input of the 0-judgment component. Since the current division operation is an invalid operation with a divisor of 0, a series of processing measures are taken according to the design requirements (for example, a warning that the divisor is 0, etc.) is taken to complete the division operation.

example 2

[0112] Example 2. In this example, assume that the division operation performed is 32-bit unsigned fixed-point division, and the dividend and divisor are 32'bit: 00000000_00000000_11111111_00000000, and 32'bit: 00000000_00001111_00000000_00000000.

[0113] The specific algorithm steps are described below:

[0114] 21) Preprocessing stage.

[0115] Firstly, it is determined that the divisor is not 0, and the division operation is an effective operation; because the division operation is an unsigned operation, there is no need to calculate the absolute value of the dividend and the divisor; after comparison, the dividend is smaller than the divisor, so the division operation enters the result processing stage.

[0116] 22) Result processing stage.

[0117] The result processing part receives the input of the preprocessing part. Since the absolute value of the dividend is smaller than the absolute value of the divisor, the quotient value can be 0, and the remainder directly take...

example 3

[0118] Example 3. In this example, assume that the division operation performed is 32-bit unsigned fixed-point division, and the dividend and divisor are 32'bit: 00000000_00000000_11111111_00000000, 32'bit: 00000000_00000000_00000000_00001111.

[0119] According to the existing traditional division operation based on subtraction and shifting, only one bit is shifted to the left each time, and then the subtraction operation is performed. The above division operation requires 32 loop operations. The optimization of the division algorithm based on subtraction and shifting in the prior art can reduce the above operation by 16 cycles, but according to the new method proposed by the present invention, after preprocessing, only two cycles are required to complete the operation. The specific method steps will be described below:

[0120] 31) Preprocessing stage.

[0121] First, it is determined that the divisor is not 0, and the division operation is a valid operation; because the di...

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PUM

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Abstract

The invention discloses a fixed-point divider and an operation processing method thereof; the divider comprises a zero judgment device for judging weather a divisor is zero; a pre-processing device for receiving an identifier which is used for indentifying weather symbol manipulation is carried out, and a dividend and the divisor, generating absolute values of the dividend and the divisor, carrying out selecting operation after the absolute values are compared and generating an identifier for processing a quotient result and a remainder and transmitting to a result processing device; a cycle shift subtractive device for controlling shifting and subtracting operation and outputting to the result processing device when the circulating is finished according to the current circle execution phase, the number of leading zero and the input operand; and the result processing device for receiving the input zero judgment processing result, the preprocessed identifier and the result of the cycleshift subtraction and outputting the quotient result and the remainder after the judgment processing is carried out. On the premise of keeping small divider area and low power consumption, the fixed-point divider has high performances.

Description

technical field [0001] The invention relates to the technical field of computer chips, in particular to a fixed-point divider and an operation processing method thereof. Background technique [0002] In modern electronic system designs, fixed-point division components are often essential. Most fixed-point division components are based on multiple considerations of timing, area, and performance. They usually use a subtraction-based loop algorithm. This algorithm is characterized in that each loop generates a quotient, and the number of loops is determined by the number of operands in the division. [0003] For example, in a 32-bit general-purpose processor, a fixed-point division requires 32 cycles to complete. [0004] Through analysis, most division operations do not need to go through so many cycles. For example, when performing an 8-bit unsigned fixed-point division operation, if the dividend is 00001000 and the divisor is 00000001, according to the traditional method, ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F7/487
Inventor 张广飞李祖松汪文祥
Owner LOONGSON TECH CORP