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Vertical channel dual-grate tunneling transistor and preparation method thereof

A vertical channel, MOS transistor technology, used in transistors, semiconductor/solid-state device manufacturing, semiconductor devices, etc., can solve the problems of reducing driving current and reducing leakage current, and achieve the effect of reducing power consumption and reducing leakage current

Inactive Publication Date: 2011-12-07
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, although the tunneling field effect transistor can be shrunk down to less than 20 nanometers, while reducing the leakage current, its driving current is also reduced.

Method used

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  • Vertical channel dual-grate tunneling transistor and preparation method thereof
  • Vertical channel dual-grate tunneling transistor and preparation method thereof
  • Vertical channel dual-grate tunneling transistor and preparation method thereof

Examples

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Embodiment Construction

[0032] An exemplary embodiment of the present invention will be described in detail below with reference to the accompanying drawings. In the drawings, the thicknesses of layers and regions are exaggerated for convenience of illustration, and the shown sizes do not represent actual sizes. Although these figures do not completely reflect the actual size of the device, they still fully reflect the mutual positions between the regions and the constituent structures, especially the upper-lower and adjacent relationships between the constituent structures.

[0033] The referenced figures are schematic illustrations of idealized embodiments of the invention, and the illustrated embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated in the figures but are to include resulting shapes, such as manufacturing-induced deviations. Also in the following description, the terms wafer and substrate used may be understood to include the s...

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Abstract

The invention belongs to the technical field of a semiconductor device, which particularly discloses a semiconductor device. The semiconductor device comprises an N type tunneling transistor and a P type MOS (Metal Oxide Semiconductor). The N type tunneling transistor adopts a vertical channel dual-grate structure. The P type MOS adopts a depressed channel structure. The invention also discloses a method for manufacturing the semiconductor device. The manufactured semiconductor device has the advantages of low drain current, high driving current and the like. The power consumption of the chipis greatly decreased by the integration circuit.

Description

technical field [0001] The technical field of semiconductor devices of the present invention, specifically relates to a semiconductor device and a manufacturing method thereof, in particular to an inverter comprising an N-type tunneling transistor adopting a vertical channel double-gate structure and a P-type MOS transistor adopting a recessed channel Integrated circuits and their manufacturing methods belong to the manufacturing technologies below the 30nm technology node. Background technique [0002] In recent years, microelectronics technology with silicon integrated circuits as the core has developed rapidly. The development of integrated circuit chips basically follows Moore's law, that is, the integration level of semiconductor chips doubles every 18 months. Today's integrated circuit device technology node is already at about 45 nanometers, the size of metal-oxide-silicon field-effect transistors (MOSFETs) is getting smaller and smaller, and the transistor density on...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/092H01L29/78H01L21/8238H01L21/336
Inventor 臧松干王鹏飞张卫
Owner FUDAN UNIV