Method of multiplexing filter operation unit and operation system of filter

Abstract

The invention provides a method for multiplexing a filter arithmetic element and a filter arithmetic system. The method comprises the following steps: 1, acquiring arithmetic data filter transmission; 2, selecting a first addend a1 and a second addend b1 in the arithmetic data, adding a1 and b1 through a summator to obtain a first adding result, and saving the first adding result to a first storage unit; 3, performing regular signed digit position encoding on coefficient h1 to obtain a numerical value N1; and 4, feeding back the first adding result of the first storage unit to the summator for N1 times for accumulation operation, saving each adding result through the second storage unit, feeding back the adding result of the second storage unit to the summator, and performing add operation with the first adding result to obtain a calculation result of h1*(a1+b1). The invention achieves the purpose of saving arithmetic resource and arithmetic amount through arithmetic element multiplexing.

Description

technical field [0001] The present invention relates to electronic circuit components, in particular to a method for multiplexing filter computing units and a filter computing system. Background technique [0002] At present, interpolation filters have been widely used in analog-to-digital conversion circuits in the field of audio signal processing to realize oversampling of input signals. In order to reduce the cost of hardware implementation, multi-stage interpolation filters are usually selected in the analog-to-digital conversion circuit, and the most commonly used one is the half-band interpolation filter. [0003] Usually, the half-band interpolation filter includes a plurality of arithmetic units, and each arithmetic unit is composed of a plurality of adders and multipliers, so as to realize high and complex computation. However, for high-bit-width arithmetic units, especially high-bit-width multipliers, the combinational logic area required is very large, and the ar...

AI Technical Summary

Problems solved by technology

However, for high-bit-width arithmetic units, especially high-bit-width multipliers, the combinational logic area required is very large, and the area required by a multiplier is usually 2 to 4 times the area required by an adder, so the interpolation filter The area of ​​the computing unit needs to be very large, and the calculation amount of the interpolation filter is also high, which greatly wastes computing resources

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