Nonvolatile semiconductor storage device
一种存储装置、非易失性的技术，应用在非易失性半导体存储装置领域，能够解决泄漏电流、处理速度变慢、限制等问题，达到低功耗的效果
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
no. 1 Embodiment
[0057] figure 1 It is a functional block diagram of the nonvolatile memory of the first embodiment of the present invention.
[0058] This nonvolatile memory has a memory core 100 . The memory core 100 includes figure 2 A plurality of memory banks (banks) arranged three-dimensionally are shown. These memory banks are formed by laminating a plurality of memory cell array layers. The memory cell array layer respectively has: in the row direction ( figure 2 A plurality of word lines WL extending in the x direction); in the column direction crossing the word lines WL ( figure 2 A plurality of bit lines BL extending in the y-direction); memory cells MC provided at respective intersections of these word lines WL and bit lines BL. Each memory cell array layer is connected to a silicon substrate disposed under the memory cell array layer via a word line contact and a bit line contact provided at one end of each word line WL and bit line BL. On this silicon substrate, logic ci...
no. 2 Embodiment
[0138] Next, a page write operation in the nonvolatile memory according to the second embodiment of the present invention will be described together with a comparative example.
[0139] Figure 35 is a diagram illustrating a page writing operation in a comparative example. Here, among write data, hatched write data indicates that there is a write bit. The written data without hatching indicates that there is no written bit (hereinafter referred to as "blank data"). Note that hatched banks represent banks to which a bias voltage is supplied when data is written. In addition, each 1 byte of data written in a unit length of 16 bytes is distributed among the 16 banks included in the memory core.
[0140] exist Figure 35 In the case of the comparative example shown, the bias voltage is supplied to all the banks regardless of whether the write data is blank data or not. In this case, even in a bank that does not require data writing, a reverse bias is applied to the non-select...
no. 3 Embodiment
[0167] In the second embodiment, whether or not data written in each bank is blank data is judged every cycle, and the supply / stop of the bias voltage is controlled. However, in this case, in addition to the complicated control, for example, when the supply of the bias voltage is stopped in the previous cycle and the supply of the bias voltage is restarted in the next cycle, it is necessary to use a Waiting time for bank reactivation. As a result, page write operations may be processed slower.
[0168] Therefore, in this embodiment, the presence or absence of written bits in all cycles is judged for each bank, and the supply of bias voltage in subsequent cycles is stopped when the written bits do not exist.
[0169] Figure 20A and Figure 20B is a diagram explaining the page writing operation in this embodiment. This figure shows the case where the page writing operation is performed in three cycles of A to C. Figure 20A The squares in are the writing units, and the squ...
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More