Duty-cycle modulated transmission
A duty-cycle modulation and duty-cycle technology, applied in transmission systems, digital transmission systems, baseband systems, etc., can solve problems such as low data rate and lower sampling clock rate, and achieve the effect of preventing the lower limit
Active Publication Date: 2010-10-06
NXP BV
View PDF4 Cites 22 Cited by
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
But the inventors have realized that if the above is also used to allow very low data rates, problems can arise as there will be very many sub-ranges needed to prevent clipping and data loss
[0009] For oversampling receivers also mentioned in the above patent application, clipping is not an issue, but that type of receiver requires the availability of a clock signal and continuous
Also, to make it more efficient, the sample clock rate needs to be reduced for low data rates, which tends to cause subrange issues like
Method used
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View moreImage
Smart Image Click on the blue labels to locate them in the text.
Smart ImageViewing Examples
Examples
Experimental program
Comparison scheme
Effect test
Embodiment Construction
[0050] A method of particular interest (i.e., a particularly advantageous embodiment of the invention) is to use a fixed length of time for short fractions of the bit period for data rates below a certain limit rate, while at the same time maintaining the use of bit periods for data rates above this limit rate. fixed part of the period, which means the duration of the scaling (in Figure 3a An example of such an implementation is schematically shown in -c).
[0051] This corresponds to a fixed duty cycle for higher rates and an increasing duty cycle for dropping the data rate below the limit rate. For example, if a fixed-duration demand is matched with a demand for a short portion of the lowest range with a fixed duty cycle, a smooth crossover is obtained (as in Figure 4a shown schematically).
[0052] In a real system, due to reflections, the minimum allowable pulse width may be determined by the interconnect length. For example, in the case of M-PHY, the expected maximum...
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More PUM
Login to View More Abstract
A duty-cycle modulated bit signalling method and circuit, comprising: signaling bits by virtue of a duty-cycle ratio; wherein the duty-cycle ratio is varied dependent upon the transmission rate of the signalling. A bit period comprises a long phase and a short phase and the duty-cycle therebetween is varied such that the ratio between the duration of the long phase and the duration of the short phase is increased for decreasing transmission rate. The duty-cycle ratio is varied dependent upon the transmission rate of the signalling according to one or more ranges of transmission rate. In a higher transmission rate range the duty-cycle is defined as a fixed ratio, and in a lower transmission range the duty-cycle is defined by a fixed length of the short phase of the bit period.
Description
technical field [0001] The present invention relates to Duty Cycle Modulation (DCM) bit signaling. Background technique [0002] like figure 1 As shown, a duty cycle modulation bit signaling scheme is described in European Patent Application 07104483.8 published as WO 2008 / 114205, which is hereby incorporated by reference. At a given bit period (at figure 1 In the example of 3T), there is a short phase 20 and a long phase 30. exist figure 1 In the example of , the duty ratio between the duration of the long phase 30 and the duration of the short phase 20 is 2:1. [0003] figure 2 An example of a fixed-rate, fixed-ratio different DCM transmission applying rising edge modulation is shown such that each bit starts with a period of negative polarity. The bitstream explicitly includes the clock. In this example, bit transfers start from a static standby state with negative line polarity, through an intermediate wake-up cycle with positive line polarity, in preparation for...
Claims
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More Application Information
Patent Timeline
Login to View More Patent Type & Authority Applications(China)
IPC IPC(8): H04L25/49H03K5/06
CPCH04L25/4902
Inventor 赫里特·威廉·登贝斯特
Owner NXP BV