Method for forming groove

Abstract

The invention discloses a method for forming a groove, which is used for etching an insulating layer of a semiconductor device to form the groove, wherein the insulating layer consists of an etch stop layer, a low dielectric constant (Low-K) insulating material layer and a hard mask layer which are formed on a semiconductor substrate in sequence. The method comprises the following steps: coating a photoresist layer on the hard mask layer; patterning the photoresist layer; etching the hard mask layer and the Low-K insulating material layer in turn by using the patterned photoresist layer as a mask in an etching reaction cavity, stopping etching in the etch stop layer to form the groove; and performing in-situ ashing treatment on the photoresist layer in two steps in the same reaction cavity, wherein the first step is to dilute residual etching gas in the etching reaction cavity by adopting nitrogen (N2), and the second step is to carry out ashing by adopting the carbon monoxide (CO) or carbon dioxide (CO2). By adopting the method, the defect of facet top profile can be effectively overcome.

Description

technical field [0001] The invention relates to the technical field of manufacturing semiconductor components, in particular to a method for forming grooves. Background technique [0002] At present, in the back-end-of-line (BEOL) process of semiconductor devices, multiple layers of metal interconnection layers can be grown on semiconductor substrates according to different needs, and each layer of metal interconnection layers includes metal interconnection lines And the insulating layer, which requires the manufacture of trenches (trench) and connection holes for the above-mentioned insulating layer, and then deposit metal in the above-mentioned trenches and connection holes, the deposited metal is the metal interconnection line, and copper is generally selected as the metal interconnection wire material. The insulating layer includes an etch stop layer formed sequentially on the semiconductor substrate, such as a nitrogen-doped silicon carbide layer; a low dielectric cons...

AI Technical Summary

Problems solved by technology

like figure 1 As shown, the junction of the TEOS layer 101 and the Low-K insulating material layer 102 does not form a smooth inner sidewall of the trench, but a stepped section appears, which prevents the subsequent formation of a barrier on the inner surface of the trench 100 by physical vapor deposition (PVD). Layers, such as the deposition of tantalum / tantalum nitride layer (Ta / TaN) (Barrier Depositon), and electrochemical plating (Electrical Chemical Plating), will cause obstacles, so it will adversely affect the electrical properties of semiconductor components

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