High performance field effect transistor and manufacturing method thereof

Abstract

The invention provides a high performance field effect transistor, comprising a substrate, a grid pile arranged above the substrate, a source / drain region which is arranged at the two sides of the grid pile and in the substrate as well as a carbon containing thin layer which is arranged between the source / drain region and the substrate. The invention adopts the carbon containing thin layer such as Si: C thin layer or SiGe: C thin layer, impurity in the source / drain region can be effectively inhibited from spreading to a channel and the substrate, thus improving the property of device.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a high-performance field effect transistor and a forming method thereof. Background technique [0002] At present, with the continuous shrinking of the feature size of field effect transistors, impurities doped with a high concentration in the source / drain regions will diffuse into the channel during the subsequent high-temperature annealing process, thereby causing deterioration of transistor performance. Therefore, the doping concentration of impurities in the source / drain regions is currently limited, for example, the doping concentration of impurity B in strained Si PMOS is lower than 10 21 cm -3 . In addition, if doped polycrystalline Si or polycrystalline SiGe is used as the gate, as the thickness of the gate dielectric layer becomes thinner, high-concentration doped impurities such as B or P can easily penetrate the gate dielectric layer. reaching the channel reg...

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Problems solved by technology

[0002] At present, with the continuous shrinking of the feature size of field effect transistors, the high-concentration doped impurities in the source / drain regions will diffuse into the channel in the subsequent high-temperature annealing process, thereby causing deterioration of transistor performance.

Therefore, the doping concentration of impurities in the source / drain regions is currently limited, for example, the doping concentration of impurity B in strained Si PMOS is lower than 10 21 cm -3

In addition, if doped polycrystalline Si or polycrystalline SiGe is used as the gate, as the thickness of the gate dielectric layer becomes thinner, high-concentration doped impurities such as B or P can easily penetrate the gate dielectric layer. reach the channel region, thereby exacerbating the deterioration of device performance

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