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Programmable device, control method of device and information processing system

一种编程设备、控制机构的技术，应用在节电化领域，能够解决不能再开始动作等问题，达到削减消耗电力的效果

Inactive Publication Date: 2011-02-09
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] However, in the prior art described above, if the power supply of the circuit block that temporarily stops operation and is in the standby state is cut off for power saving, even the configuration information defining the operation of the circuit block is also transferred from the SRAM (Static Random Access Memory: Static Random Access Memory). Random access memory) disappears, and the configuration information needs to be set again when power is supplied thereafter, so there is a problem that the operation cannot be restarted immediately from the state before standby

Method used

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  • Programmable device, control method of device and information processing system
  • Programmable device, control method of device and information processing system
  • Programmable device, control method of device and information processing system

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Embodiment approach 1

[0073] 1.1. Structure

[0074] figure 1 It is a block diagram showing the processing system 1 according to one embodiment of the present invention.

[0075] The processing system 1 includes a programmable device 2 , an external storage unit 3 that stores configuration information (Config) of circuits in the programmable unit 2 , and a power supply unit 4 .

[0076] The programmable device 2 includes a plurality of programmable processing blocks (tiles) 11 (11a, 11b...11i) which are logical processing units, and a configuration control mechanism 13 for distributing the above-mentioned configuration information to each processing block 11 for programming. , a power control unit 12 for controlling the power output from the power supply unit 4 , and power supply wirings 14 to 16 .

[0077] In addition, the processing blocks 11a to 11i include a configuration memory 21 that holds the above-mentioned configuration information, a core logic 22 that performs calculation processing a...

Embodiment approach 2

[0170] In Embodiment 1, such as Figure 7 As shown in (b), when allocating user circuits to programmable devices, not all processing blocks are necessarily used, and some processing blocks are unused areas 209 according to the allocation method.

[0171] Although it is not necessary to supply power to the processing block which is the unused area 209 , in the configuration of the processing system according to Embodiment 1, the power supply to the allocation memory cannot be cut off.

[0172] In addition, the configuration memory may be composed of low-leakage transistors, but if its capacity is increased, the leakage power as a whole may not be ignored.

[0173] Therefore, in Embodiment 2, it is possible to configure a programmable device by shutting off the power supply to the allocation memory of the above-mentioned unused processing block, thereby achieving further power saving.

[0174] Hereinafter, the difference from Embodiment 1 will be mainly described.

[0175] 2.1...

Embodiment approach 3

[0194] In Embodiment 2, the user circuit is Figure 7 Functional allocation as shown in (b), such as Figure 7 (c) Operate in such a way that only one module becomes active at the same time. In this case, most of the devices are in an inactive standby state, and the utilization efficiency of circuit resources is low.

[0195] The programmable device according to Embodiment 3 is a dynamically reconfigurable device whose configuration can be changed during operation.

[0196] Specifically, as Figure 12 As shown, for one device 400, the processing is performed while dynamically allocating the module A (401), the module B (402), and the module C (403) in a time-division manner.

[0197] Here, when changing the configuration from module A (401) to module B (402), even if the internal state of the processing block belonging to module A (401) is saved in the corresponding (stored and initialized In the memory unit of the structure information), since the configuration informatio...

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Abstract

A programmable device which can operate at high speed while reducing power consumption. The programmable device (2) comprises a plurality of processing tiles (11) each including a constitution memory (21) and a core logic (22), a constitution control means (13) for programming them, and a power control means (12) for interrupting power supply depending on the operating state of them. Power supply of the core logic (22) is interrupted after evacuating the internal state of the core logic (22) to the constitution memory (21), and power is supplied again to the core logic (22) before the internal state is reset from the constitution memory (21) to the core logic (22) thus saving power while maintaining the internal state.

Description

technical field [0001] The present invention relates to power saving of programmable devices. Background technique [0002] In recent years, dynamically reconfigurable devices have been developed that can change their structure within a short period of several microseconds to several nanoseconds even during operation (see Non-Patent Document 1). [0003] In the case of increasing the speed and miniaturization of the above-mentioned devices, leakage power which accounts for about 50% of the total power consumption of the chip may become a problem. [0004] As a countermeasure against the above-mentioned problems, Patent Document 1 discloses a technique of cutting off power supply to unused or standby circuit blocks that have no function assigned to them, using a power gating technique. [0005] Patent Document 1: U.S. Patent No. 7,098,689 [0006] Non-Patent Document 1: Masato Motomura, "A Dynamically Reconfigurable Processor Architecture", Microprocessor Forum, Oct, 2002 ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/822H03K19/00H01L21/82H01L27/04H03K19/177
CPCH03K19/17784H03K19/17772
Inventor 西冈伸一郎
Owner PANASONIC CORP