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Memory multimode access control method and SRAM memory control system on chip

An access control and control system technology, applied in the field of image encoding and decoding, can solve the problems of low reading and writing efficiency and poor flexibility of image storage, and achieve the effect of flexible access mode, switching access mode, and improving read and write efficiency

Inactive Publication Date: 2011-04-20
ZHEJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0017] In order to overcome the deficiencies of the existing memory access mechanism, such as poor flexibility, no transpose storage function, and low image storage read-write efficiency, the present invention provides a device that can flexibly switch access modes, has a transpose storage function, and improves image storage read-write efficiency. Memory multi-mode access control method and its memory control system

Method used

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  • Memory multimode access control method and SRAM memory control system on chip
  • Memory multimode access control method and SRAM memory control system on chip
  • Memory multimode access control method and SRAM memory control system on chip

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Embodiment 1

[0056] refer to Figure 3 to Figure 10 , a memory multi-mode access control method, the Figure 5 Each 4×4 block in a 16×16 macroblock shown is divided into 4 lines, respectively a, b, c, d, and each line consists of 4 bytes (8-bit data is called a word section) data composition. Then the access control process is as follows:

[0057] In the inverse quantization and inversion (IQIT) mode, each clock cycle generates 32-bit data consisting of 4 pixels in a column and writes them into the on-chip SRAM. Generate each column of block 0 in order, then generate each column of block 1, until each column of block 15 is also generated, and then start the generation of the next macroblock. The generation order of the columns in the block is as follows: First generate the 32- bit data, and regenerate the k+1th byte of a line, the k+1th byte of b line, the k+1th byte of c line, and the k+1th byte of d line 32-bit data.

[0058] In deblocking filter (DF) mode, each clock cycle reads 3...

Embodiment 2

[0078] refer to Figure 3 to Figure 10 , a kind of memory control system, is made up of 2 blocks of SRAM, and 2 blocks of SRAM are arranged according to the overall order, and the global address block is arranged according to the order that two SRAM address blocks alternately increase; A bit segment selection generation unit, an address decoding unit, an input data allocation unit and an output data combination unit.

[0079] In order to better design the controller module, various modes can be divided into address mode and transposition mode. In the inverse quantization and inverse transformation (IQIT) mode, according to the storage access mechanism introduced earlier, each time is accessed column by column, and the block is not accessed in the order of row by row, so it belongs to the transpose mode; since each access is 1 column 32-bit data, so compared to the default mode, the address mode is special. In deblocking filter (DF) mode, there is no transposition due to acce...

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Abstract

The invention provides a memory multimode access control method. Each 4*4 block in a 16*16 macro block in image data is divided into a, b, c and d rows, and each row comprises four-byte data. The access control method comprises the following processes: under an inverse quantization inverse transformation mode and a deblocking filtered mode, read and write operation of SRAM (Static Random Access Memory) on a chip is carried out by a memory mechanism of a memory mode of a direct memory under a default mode according to a chip selection enable signal, a write enable signal, a write bit segment selective signal, an address input signal and a data input signal which are provided externally. A memory control system which realizes the multimode access control method is also provided. The memory multimode access control method which can flexibly switch access modes, has a transposition memory function and improves the image storage read and write efficiency and the memory control system are provided by the invention.

Description

technical field [0001] The invention relates to the field of image coding and decoding, in particular to a memory control method and a control system for image coding and decoding processing. Background technique [0002] H.264 is a video coding standard jointly formulated by the International Telecommunication Standardization Sector (ITU-T) and the International Organization for Standardization (ISO) / International Electrotechnical Commission (IEC) that formulated MPEG, in order to achieve high video compression ratio and high image quality. Quality, good network adaptability. H.264 is also known as MPEG-4AVC ("Moving Picture Experts Group-4 Advanced Video Coding") or MPEG-4 Part10. Because of its excellent performance compared with previous standards, it is called a new generation of video coding standards, and has been widely valued and welcomed in the world. The hardware design of the H.264 decoder has become a research hotspot. The flow chart of a typical H.264 decoder...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/28G06F12/06
Inventor 严晓浪修思文黄凯马德
Owner ZHEJIANG UNIV